Skip to content

Operator Coverage

heliaRT provides three kernel backends. Every operator has a Reference implementation. The CMSIS-NN and HELIA columns show where optimized implementations replace the generic code.

How to read this table

  • REF = Reference (generic C, all architectures)
  • CMSIS = open-source Arm CMSIS-NN (Cortex-M only)
  • HELIA = Ambiq-optimized heliaCORE (Cortex-M only)
  • ✅ = optimized kernel exists
  • = falls back to Reference

These columns are data-type agnostic: a ✅ means an optimized kernel exists for at least one data type. Most entries cover int8 and int16. For the floating-point picture, see Floating-Point Coverage below.

Compute Operators

Operator REF CMSIS HELIA Notes
CONV_2D ✅ ✅ ✅
DEPTHWISE_CONV_2D ✅ ✅ ✅
FULLY_CONNECTED ✅ ✅ ✅ HELIA adds A16W16 path
TRANSPOSE_CONV ✅ ✅ ✅
BATCH_MATMUL ✅ ✅ ✅
SVDF ✅ ✅ ✅
UNIDIRECTIONAL_SEQUENCE_LSTM ✅ ✅ ✅

Pooling & Padding

Operator REF CMSIS HELIA Notes
AVERAGE_POOL_2D / MAX_POOL_2D ✅ ✅ ✅
PAD / PADV2 ✅ ✅ ✅
SOFTMAX ✅ ✅ ✅
TRANSPOSE ✅ ✅ ✅
MAXIMUM / MINIMUM ✅ ✅ ✅

Activations

Operator REF CMSIS HELIA Notes
RELU / RELU6 / RELU_N1_TO_1 ✅ ✅ HELIA-exclusive
LOGISTIC (sigmoid) ✅ ✅ HELIA-exclusive
TANH ✅ ✅ HELIA-exclusive
LEAKY_RELU ✅ ✅ HELIA-exclusive
HARD_SWISH ✅ ✅ HELIA adds int16 path

Arithmetic

Operator REF CMSIS HELIA Notes
ADD ✅ ✅ ✅
MUL ✅ ✅ ✅
SUB ✅ ✅ HELIA-exclusive
EQUAL / NOT_EQUAL / GREATER / LESS / etc. ✅ ✅ HELIA-exclusive

Data Movement

Operator REF CMSIS HELIA Notes
CONCATENATION ✅ ✅ HELIA-exclusive
RESHAPE ✅ ✅ HELIA-exclusive
SPLIT ✅ ✅ HELIA-exclusive
SPLIT_V ✅ ✅ HELIA-exclusive
PACK ✅ ✅ HELIA-exclusive
SQUEEZE ✅ ✅ HELIA-exclusive
STRIDED_SLICE ✅ ✅ HELIA-exclusive
FILL ✅ ✅ HELIA-exclusive
ZEROS_LIKE ✅ ✅ HELIA-exclusive
DEQUANTIZE ✅ ✅ HELIA-exclusive

Quantization

Operator REF CMSIS HELIA Notes
QUANTIZE ✅ ✅ HELIA-exclusive (common path)

Reduce

Operator REF CMSIS HELIA Notes
MEAN / REDUCE_MAX ✅ ✅ HELIA-exclusive

Floating-Point Coverage

The HELIA backend also dispatches FP32 and FP16 operators to heliaCORE. These paths are gated at build time by ARM_NN_ENABLE_F32 / ARM_NN_ENABLE_F16. The Make build and the published static libraries always enable FP32 (plus FP16 on Cortex-M55), NSX requires FP32, and Zephyr implies both from the target; only standalone CMake is fully opt-in. See the FP16 and FP32 guide for how each build system resolves them.

FP32 and FP16 degrade differently

FP32 falls back to the Reference kernel whenever the optimized kernel is disabled or rejects a configuration — results stay correct, only slower. Most FP16 operators have no TFLM Reference implementation (pure data movement such as TRANSPOSE and RESHAPE is the exception). Where a limitation is known at graph preparation the operator fails AllocateTensors(); otherwise it returns kTfLiteError from Invoke(), in most cases with a logged diagnostic.

FP16 additionally requires Armv8.1-M with MVE floating point (Cortex-M55). It is not available on Cortex-M4+FP.

Operator FP32 FP16 Constraints
CONV_2D ✅ ✅ Grouped convolution is not supported by the optimized kernels: FP32 uses Reference, FP16 is rejected at prepare
DEPTHWISE_CONV_2D ✅ ✅
FULLY_CONNECTED ✅ ✅
TRANSPOSE_CONV ✅ ✅
BATCH_MATMUL ✅ ✅
SVDF ✅ ✅
UNIDIRECTIONAL_SEQUENCE_LSTM ✅ ✅ Standard four-gate LSTM only; peephole, projection, layer-norm and CIFG variants use Reference (FP32) or are rejected (FP16). Hidden/cell state carry across invocations requires ns-cmsis-nn v7.29.0+
AVERAGE_POOL_2D / MAX_POOL_2D ✅ ✅ 4-D tensors only
SOFTMAX ✅ ✅ beta == 1.0 only; other values use Reference (FP32) or are rejected at prepare (FP16)
PAD / PADV2 ✅ ✅ FP16 requires 4-D tensors, enforced at prepare
TRANSPOSE ✅ ✅ Optimized for rank ≤ 4; higher ranks use Reference (float path for FP32, bitwise 16-bit path for FP16). FP16 works even without ARM_NN_ENABLE_F16
MAXIMUM / MINIMUM ✅ ✅ Optimized for rank ≤ 4; higher ranks use Reference (FP32)
ADD ✅ ✅ FP16 requires matching input shapes; broadcasting is rejected at prepare
MUL ✅ ✅ FP16 requires matching input shapes; broadcasting is rejected at prepare
CONCATENATION ✅ ✅ Optimized for rank ≤ 4; higher ranks use the Reference path (FP32 and FP16)
RESHAPE ✅ ✅ Pure data movement; FP16 works even without ARM_NN_ENABLE_F16 via a bitwise copy
RELU / RELU6 ✅ ✅
LOGISTIC (sigmoid) ✅ ✅
TANH ✅ ✅

Other operators use the Reference implementation for FP32, with one exception: QUANTIZE and DEQUANTIZE always convert through optimized heliaCORE kernels on their float32 side, independent of ARM_NN_ENABLE_F32. The published static libraries ship FP32 kernels for Cortex-M4+FP and both FP32 and FP16 for Cortex-M55.

Summary

Backend Optimized kernels Coverage
Reference 109 All operators (generic C)
CMSIS-NN 14 Core compute-heavy ops
HELIA 36 Superset of CMSIS-NN + 22 additional

HELIA advantage

HELIA covers every operator that CMSIS-NN does, plus 22 additional operators that would otherwise fall back to slow Reference kernels. This means fewer "silent fallbacks" and more consistent performance across your entire model.

Next Steps