Search the HELIA adapter inventory by operator, family or input data type. Each result lists important constraints and links to the adapter at this documentation’s source revision.
A listed type can use an optimized, reference or storage-only path. Shape, weight/output types and build settings still determine whether your model is supported.
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FP32, int8 and quantized int16 run CORE; quantized scaling requirements apply. Unquantized int16 uses Reference, which wraps -32768. FP16 requires ARM_NN_ENABLE_F16; without it preparation fails.
Adapter sourceFloat identical-shape inputs support arbitrary rank. Optimized broadcasting supports rank <= 4; higher-rank FP32 uses Reference and FP16 is rejected. int32 follows the adapter reference path.
Adapter sourceint8 runs CORE, FP32 runs CORE with ARM_NN_ENABLE_F32 and FP16 with ARM_NN_ENABLE_F16, at rank 1..4 with INT32 axis/output and positive reduced extent; other configurations use Reference (FP16 is rejected). A NaN never wins and ties keep the first index.
Adapter sourceint8 runs CORE, FP32 runs CORE with ARM_NN_ENABLE_F32 and FP16 with ARM_NN_ENABLE_F16, at rank 1..4 with INT32 axis/output and positive reduced extent; other configurations use Reference (FP16 is rejected). A NaN never wins and ties keep the first index.
Adapter sourceFour-dimensional tensors; check filter/stride/padding and output dimensions. Kernel failure is returned to the application.
Adapter sourceCheck batch broadcasting, adjoint flags and quantized weight/activation combinations against the adapter.
Adapter sourceOptimized float paths support rank <= 4; higher-rank float inputs use Reference. Input/output type and quantization must agree.
Adapter sourceQuantized weight/bias combinations are constrained. int4 weights use int8 activations. Float grouped convolution uses Reference for FP32 and is rejected for FP16.
Adapter sourceReference implementation in the HELIA adapter source; Float32 input/output.
Adapter sourceQuantized weight/bias combinations and depth multiplier are constrained. int4 is a weight type with int8 activations; it is not a general activation type. Register_DEPTHWISE_CONV_2D_FLOAT16_ACC16() is an opt-in registration that accumulates float16 layers in float16 lanes on MVE; see the floating-point guide.
Adapter sourceOutput is FP32. A per-tensor int8 or int16 input runs on heliaCORE. An int8 or uint8 input may be per-channel (one scale and zero point per channel along any quantized dimension) and is dequantized with each channel's own parameters, matching TensorFlow Lite; a per-channel int16 input is rejected at Prepare (TensorFlow Lite rejects it at Invoke). FP16 means weight-storage widening, not FP16 computation; it calls arm_dequantize_f16_bits_f32 on every target, works without ARM_NN_ENABLE_F16, and matches the reference widening bit for bit at reset FPSCR: a NaN keeps its sign and payload and comes back quiet, on the MVE path too. On cores with an FPU but no MVE float16 (for example cortex-m4+fp) the widening runs on the FPU, so with FPSCR.DN (default NaN) set every NaN becomes 0x7FC00000.
Adapter sourceFP32 and FP16 run CORE for identical shapes and rank <= 4 broadcasts; other FP32 shapes use Reference and FP16 is rejected. int8 and int32 use Reference. FP16 requires ARM_NN_ENABLE_F16; without it preparation fails.
Adapter sourceBoolean output. Supported input types depend on the comparison; input shapes and broadcast rules must match.
Adapter sourceConstant dimensions and scalar fill value. Float APIs require CORE >= 7.33.0 and matching enabled feature.
Adapter sourceQuantized activation/weight/bias types must match a supported combination; includes int4 weights with int8 activations. Float paths require matching CORE features.
Adapter sourceCORE >= 7.34.0. Native rank <= 4. Scalar indices use float native paths or int8 Reference; int16 rejects them. Higher-rank FP32/int8 use Reference; FP16/int16 reject.
Adapter sourceCORE >= 7.34.0. Native ranks <= 4 and positive index tuple width. Higher ranks and zero-width tuples use FP32/int8 Reference; FP16/int16 reject.
Adapter sourceBoolean output. Check broadcast and operand types; no FP16 comparison branch.
Adapter sourceBoolean output. Check broadcast and operand types; no FP16 comparison branch.
Adapter sourceFP16 requires the CORE float feature; without it preparation fails. FP32 can use Reference.
Adapter sourceFloat32 uses the reference path. No FP16 execution branch in this adapter.
Adapter sourceBoolean output. Check broadcast and operand types; no FP16 comparison branch.
Adapter sourceBoolean output. Check broadcast and operand types; no FP16 comparison branch.
Adapter sourceReference implementation in the HELIA adapter source; Float32 input/output.
Adapter sourceReference boolean operation.
Adapter sourceint8 uses a lookup table; int16 and enabled floats have HELIA paths. NaN is not supported by the optimized float activation path.
Adapter sourceOptimized paths support rank <= 4. Higher-rank FP32/int8/int16 use Reference; FP16 is rejected. int32/int64 use Reference.
Adapter sourceFour-dimensional tensors; check filter/stride/padding and output dimensions. Kernel failure is returned to the application.
Adapter sourceFloat optimized paths support rank <= 4 and axis sets; higher-rank FP32 uses Reference, FP16 is rejected. On every route and dtype, an output whose element count differs from the input's elements on the kept axes, an axis outside the input rank, or an input above rank 5, fails at Invoke; a scalar input ignores its axes, as in TFLite, FP16 included. An input whose nonzero extents multiply past INT32_MAX fails there too, even when another extent is 0. An empty input runs no kernel: every output element gets 0, the value TFLite's reference writes, quantized types included. See reduce_common.cc.
Adapter sourceOptimized paths support rank <= 4. Higher-rank FP32/int8/int16 use Reference; FP16 is rejected. int32/int64 use Reference.
Adapter sourceFloat identical-shape inputs support arbitrary rank. Optimized broadcasting supports rank <= 4; higher-rank FP32 uses Reference and FP16 is rejected. int32 follows the adapter reference path.
Adapter sourceFP32 and FP16 run CORE as sign-bit flips, NaN payloads kept. FP16 requires ARM_NN_ENABLE_F16; without it preparation fails.
Adapter sourceBoolean output. Supported input types depend on the comparison; input shapes and broadcast rules must match.
Adapter sourceEqual input shapes, including scalars. Float APIs require CORE >= 7.33.0 and matching enabled feature.
Adapter sourceFP16 requires four-dimensional tensors and the float feature. Padding values and output shape must match.
Adapter sourceFP16 requires four-dimensional tensors and the float feature. Padding values and output shape must match.
Adapter sourceint8, FP32 and FP16 run CORE when the output has the input shape, alpha broadcasts into it and rank <= 4; other FP32/int8 shapes use Reference and FP16 is rejected, except an empty FP16 tensor, which is a no-op. int16 uses Reference (int8 alpha). The output type must match the input type, an FP32 input needs an FP32 alpha, and preparation fails unless the output is the broadcast shape of input and alpha with rank <= 4. FP16 requires ARM_NN_ENABLE_F16; without it preparation fails.
Adapter sourceSupported input/output pairs are specific: this type list does not imply all pairings. Registration is supplied by kernels/quantize.cc.
Adapter sourceBoolean reduction using Reference in reduce_common.cc. On every route and dtype, an output whose element count differs from the input's elements on the kept axes, or an axis outside the input rank, fails at Invoke; a scalar input ignores its axes, as in TFLite. An input whose nonzero extents multiply past INT32_MAX fails there too, even when another extent is 0.
Adapter sourceint8/int16 run CORE at rank <= 4 with equal input/output quantization. FP32 runs CORE (arm_reduce_max_tflite_f32) at rank <= 4 with ARM_NN_ENABLE_F32 and Reference otherwise; FP16 runs CORE (arm_reduce_max_tflite_f16) at rank <= 4 and is rejected otherwise or without ARM_NN_ENABLE_F16. Both follow TFLite: a NaN is skipped, a window of NaNs, of -Inf only or an empty one gives the start value (-FLT_MAX, -65504 for FP16), and an empty axis list folds each element into it. On every route, dtype and rank, an output whose element count differs from the input's elements on the kept axes, or an axis outside the input rank, fails at Invoke; a scalar input ignores its axes, as in TFLite, FP16 included. An input whose nonzero extents multiply past INT32_MAX fails there too, even when another extent is 0. An empty input runs no kernel and every output element gets the start value. Implementation is in reduce_common.cc.
Adapter sourceint8/int16 run CORE at rank <= 4 with equal input/output quantization. FP32 runs CORE (arm_reduce_min_tflite_f32) at rank <= 4 with ARM_NN_ENABLE_F32 and Reference otherwise; FP16 runs CORE (arm_reduce_min_tflite_f16) at rank <= 4 and is rejected otherwise or without ARM_NN_ENABLE_F16. Both follow TFLite: a NaN is skipped, a window of NaNs, of +Inf only or an empty one gives the start value (+FLT_MAX, +65504 for FP16), and an empty axis list folds each element into it. On every route, dtype and rank, an output whose element count differs from the input's elements on the kept axes, or an axis outside the input rank, fails at Invoke; a scalar input ignores its axes, as in TFLite, FP16 included. An input whose nonzero extents multiply past INT32_MAX fails there too, even when another extent is 0. An empty input runs no kernel and every output element gets the start value. Implementation is in reduce_common.cc.
Adapter sourceCheck activation bounds, tensor shape and quantization. Optimized float paths require the matching CORE feature.
Adapter sourceCheck activation bounds, tensor shape and quantization. Optimized float paths require the matching CORE feature.
Adapter sourcePreserves storage and element count. FP16 storage works without float arithmetic enabled. Types listed here are representative fixed-width storage types.
Adapter sourceRuns CORE, bit-exact with the reference for every align_corners/half_pixel_centers setting; layers with an empty extent use Reference and FP16 is rejected there. Preparation fails unless the output matches the input type and has shape [N, size[0], size[1], C], and fails for an empty input height or width with a nonempty output. Needs an (height + width) int32 scratch. FP32 uses Reference without ARM_NN_ENABLE_F32. FP16 requires ARM_NN_ENABLE_F16; without it preparation fails.
Adapter sourceFP32 and FP16 run CORE; integer paths use Reference. int16 must be affine-quantized with zero zero points; unquantized int16 is rejected at preparation. FP16 requires CORE >= 7.33.0 and ARM_NN_ENABLE_F16; input/output shapes and types must match. A negative input gives the positive quiet NaN.
Adapter sourceReference implementation in the HELIA adapter source; Float32 input/output.
Adapter sourceOptimized float path requires beta = 1. Other beta values use FP32 Reference or fail FP16 preparation. int8-to-int16 output has a dedicated registration.
Adapter sourceConstant axis and equal output extents. Float APIs require CORE >= 7.33.0 and corresponding enabled feature.
Adapter sourceConstant axis and split sizes; one inferred -1 size and zero-length pieces are allowed. Shapes/types/counts are checked during preparation. Float APIs require CORE >= 7.33.0.
Adapter sourceFP32 and FP16 run CORE. FP16 requires CORE >= 7.33.0 and ARM_NN_ENABLE_F16; input/output shapes and types must match. A negative input gives the positive quiet NaN.
Adapter sourceReference implementation in the HELIA adapter source; Float32 input/output.
Adapter sourceint8/int16 run CORE for identical shapes and rank <= 4 broadcasts. FP32 runs CORE for identical shapes, keeping subnormal results on the Helium path as well, and uses Reference for broadcasts. The Reference keeps subnormal results on GCC builds; clang builds (ATfE, armclang) may vectorize its loop with Helium, which flushes them. FP16 runs CORE for identical shapes and rejects broadcasts. int32 uses Reference. FP16 requires ARM_NN_ENABLE_F16; without it preparation fails.
Adapter sourceBitwise storage copy; removes unit dimensions, checks matching byte counts and rejects strings. Input rank <= 8.
Adapter sourceint8, int16 and int32 run CORE; FP32 runs CORE with ARM_NN_ENABLE_F32 and Reference without it; FP16 runs CORE with ARM_NN_ENABLE_F16 and fails preparation without it; bool uses Reference. Rank is limited to 4. For every type, an input axis above 2^30 or an input above INT32_MAX elements fails at Invoke, however small the slice; otherwise an empty slice writes nothing and succeeds, and a nonempty slice whose output element count differs from the slice's fails at Invoke. The input and output types must match.
Adapter sourceFloat identical-shape inputs support arbitrary rank. Optimized broadcasting supports rank <= 4; higher-rank FP32 uses Reference and FP16 is rejected. int32 follows the adapter reference path.
Adapter sourceSUM is LiteRT REDUCE_SUM. Float optimized paths support rank <= 4 and axis sets; higher-rank FP32 uses Reference, FP16 is rejected. On every route and dtype, an output whose element count differs from the input's elements on the kept axes, an axis outside the input rank, or an input above rank 5, fails at Invoke; a scalar input ignores its axes, as in TFLite, FP16 included. An input whose nonzero extents multiply past INT32_MAX fails there too, even when another extent is 0. An empty input runs no kernel: every output element gets 0, the value TFLite's reference writes, quantized types included. See reduce_common.cc.
Adapter sourceData input is int8, FP32 or enabled FP16. int16 is a time-weight/state type, not a supported data input type. Variable state persists across invocations; weight types, rank and activation configuration are constrained.
Adapter sourceNaN is not supported by the optimized float activation path. Float support is build-gated.
Adapter sourceOptimized rank <= 4. Higher ranks use Reference; FP16 has a bitwise storage fallback even with its float feature disabled.
Adapter sourceCheck output shape, padding and quantized weight/bias combinations. Float features are build-gated.
Adapter sourceStandard four-gate LSTM only. Preparation rejects peephole, projection, layer normalization and missing gates (CIFG), including FP32. Quantized inputs use int8 weights and int16 cell state. Preserve variable state across invocations.
Adapter sourceOne output per selected axis element. Float APIs require CORE >= 7.33.0 and matching enabled feature.
Adapter sourceFills output storage with zero; no FP16 execution branch.
Adapter sourceDownload the complete operator inventory as Markdown, including input types, constraints and source links.