Function arm_nn_activation_f16

• Defined in File arm_nnfunctions_flt.h

Function Documentation

arm_cmsis_nn_status arm_nn_activation_f16(const float16_t *input, float16_t *output, int32_t size, arm_nn_activation_type_flt type, float16_t act_param)

Elementwise activation.

Note

The RELU, RELU6 and LEAKY_RELU legs classify NaN on the integer bit pattern (#380 / #382), so a NaN input comes back as NaN at every optimization level on the gated toolchains, including the shipped -Ofast. This holds on both the scalar and the MVE (cortex-m55) build paths; the MVE RELU/RELU6 legs restore the NaN lanes that vmaxnmq/vminnmq suppress. SIGMOID, TANH and HARDSWISH are outside this contract; see the per-helper notes in Include/Internal/arm_nn_activation_flt.h.

Note

The HARDSWISH leg’s scalar helper (arm_nn_hardswish_scalar_f32, serving every build that does not take the MVE float path — no MVE float support, or MVE present but not used, e.g. under ARM_MATH_AUTOVECTORIZE) keeps the legacy separately rounded multiply-and-add gate and can differ by an ulp in the curved region from the standalone arm_hard_swish_f32, whose gate is a correctly rounded fma; the mux’s MVE helper (arm_nn_vhardswish_mve_f32) uses vfmaq and agrees with that kernel. Callers that need bit-exact, leg-agreeing hard swish — or the documented NaN/Inf contract — should call arm_hard_swish_f32 directly.

Note

The RELU, RELU6 and LEAKY_RELU legs classify NaN on the integer bit pattern (#380 / #382), so a NaN input comes back as NaN at every optimization level on the gated toolchains, including the shipped -Ofast. This holds uniformly across build paths: the scalar path serves every build without MVE float16 (and LEAKY_RELU on MVE builds too), while the MVE RELU/RELU6 legs (cortex-m55) restore the NaN lanes that vmaxnmq/vminnmq suppress, using the same integer-domain lane classification as the elementwise clamps. SIGMOID, TANH and HARDSWISH are outside this contract; see the per-helper notes in Include/Internal/arm_nn_activation_flt.h.

Note

Both legs of the HARDSWISH mux evaluate natively in float16 — the scalar helper (arm_nn_hardswish_scalar_f16) with a separately rounded multiply-and-add gate, the MVE helper (arm_nn_vhardswish_mve_f16) with a float16 vfmaq — so either can differ by an ulp from the scalar leg of the standalone arm_hard_swish_f16, which computes in float32 with an fma gate and rounds to float16 once. Callers that need the documented NaN/Inf contract should call arm_hard_swish_f16 directly.

Parameters:

• input – [in] Pointer to the input samples.

• output – [out] Pointer to the output samples.

• size – [in] Number of elements to process.

• type – [in] Activation selector.

• act_param – [in] Extra activation parameter. Used for parameterized activations such as leaky ReLU.

Returns:

ARM_CMSIS_NN_SUCCESS on success or ARM_CMSIS_NN_ARG_ERROR on invalid arguments.