Function arm_nn_mat_mult_nt_n_packed_f16

Function Documentation

arm_cmsis_nn_status arm_nn_mat_mult_nt_n_packed_f16(const float16_t *lhs, const float16_t *rhs_packed, const float16_t *bias, float16_t *dst, int32_t lhs_rows, int32_t rhs_rows, int32_t rhs_cols, int32_t row_address_offset, float16_t activation_min, float16_t activation_max)

Matrix multiply with non-transposed lhs and packed non-transposed rhs (float16).

Note

On non-MVE builds the output clamp is the bit-classified scalar clamp of #380, so a NaN accumulator (a NaN in lhs, rhs_packed or bias) propagates to dst at every optimization level on the gated toolchains, including the shipped -Ofast. On MVE builds the clamp is vmaxnmq/vminnmq with no NaN restore, so a NaN resolves to a clamp bound there instead.

Note

Accumulation width per leg: the MVE leg accumulates in float16 lanes (one lane per output column, per-k); the scalar leg (non-MVE builds and ARM_MATH_AUTOVECTORIZE) accumulates bias and every product in float32 and rounds to float16 once before the clamp (AmbiqAI/ns-cmsis-nn#449, #457).

Parameters:

  • lhs – [in] Left-hand matrix stored row-major with logical shape [lhs_rows, rhs_cols].

  • rhs_packed – [in] Right-hand matrix with logical shape [rhs_cols, rhs_rows], packed in column blocks of 8. The final block uses the same packed stride and inactive tail lanes are ignored.

  • bias – [in] Optional bias vector.

  • dst – [out] Output matrix.

  • lhs_rows – [in] Number of rows in lhs.

  • rhs_rows – [in] Number of logical output columns in the unpacked rhs matrix.

  • rhs_cols – [in] Shared reduction dimension K.

  • row_address_offset – [in] Output row stride, expressed in elements.

  • activation_min – [in] Lower clamp bound.

  • activation_max – [in] Upper clamp bound.

Returns:

ARM_CMSIS_NN_SUCCESS on success or ARM_CMSIS_NN_ARG_ERROR on invalid arguments.