Function arm_depthwise_nhwc_conv_f16

Function Documentation

arm_cmsis_nn_status arm_depthwise_nhwc_conv_f16(const cmsis_nn_context *ctx, const cmsis_nn_dw_conv_params_f16 *dw_conv_params, const cmsis_nn_dims *input_dims, const float16_t *input, const cmsis_nn_dims *filter_dims, const float16_t *kernel, const cmsis_nn_dims *bias_dims, const float16_t *bias, const cmsis_nn_dims *output_dims, float16_t *output)

Depthwise convolution, NHWC layout.

Note

When ctx->buf is used for internal kernel repacking, it must be aligned to the element type stored in scratch: at least 4-byte aligned for float32_t and at least 2-byte aligned for float16_t.

Note

Accumulation and NaN, per leg (AmbiqAI/ns-cmsis-nn#448). Every route accumulates the bias and every tap in float32 on every leg. A NaN input tap or weight does not propagate: the ch_mult == 1 direct kernel’s MVE leg clamps it to the activation minimum (vmaxnm / vminnm); the MVE to-convolution route (input channels 1, output channels 8 or more, ctx supplied) clamps it to the activation minimum (arm_nn_clamp_mve_f32); its scalar leg and the ch_mult > 1 generic kernel clamp it to the activation maximum (ARM_NN_CLAMP). That is the pre-#448 behavior of these routes; unifying it with the float16 scalar leg under the #334 promise is a separate issue.

Note

Accumulation and NaN, per leg (AmbiqAI/ns-cmsis-nn#448). MVE leg: the ch_mult == 1 direct kernel accumulates the bias and every tap in float16 lanes (#446) and clamps a NaN to the activation minimum (vmaxnm / vminnm). Scalar leg (non-MVE builds and ARM_MATH_AUTOVECTORIZE): the direct kernel accumulates in float32 and rounds to float16 once at the store (#449), and a NaN propagates through arm_nn_clamp_scalar_f16 — unlike the float32 scalar leg, which clamps it to a bound. The MVE to-convolution route (input channels 1, output channels 8 or more, ctx supplied) clamps a NaN to the activation minimum (arm_nn_clamp_mve_f16). The ch_mult > 1 generic kernel accumulates in float16 and clamps a NaN to the activation maximum (arm_nn_clamp_f16h) on every leg. Unifying these under the #334 promise is a separate issue.

Parameters:

  • ctx – [inout] Function context that may hold a temporary scratch buffer.

  • dw_conv_params – [in] Depthwise convolution parameters (stride, padding, dilation, channel multiplier and activation clamp).

  • input_dims – [in] Input tensor dimensions in NHWC format.

  • input – [in] Pointer to the input tensor data.

  • filter_dims – [in] Filter tensor dimensions in NHWC-compatible depthwise format.

  • kernel – [in] Pointer to the filter tensor data.

  • bias_dims – [in] Bias tensor dimensions. Format: [C_OUT].

  • bias – [in] Optional bias tensor data.

  • output_dims – [in] Output tensor dimensions in NHWC format.

  • output – [out] Pointer to the output tensor data.

Returns:

ARM_CMSIS_NN_SUCCESS on success or ARM_CMSIS_NN_ARG_ERROR on invalid arguments.