Elementwise Functions

Elementwise add and multiplication functions.

Machine-readable model

• arm_elementwise_add_f32functionElementwise add with optional output clamp.
• arm_elementwise_sub_f32functionElementwise subtract with optional output clamp.
• arm_elementwise_squared_difference_f32functionElementwise squared difference of contiguous FP32 vectors.
• arm_nn_abs_f32functionElementwise absolute value.
• arm_nn_neg_f32functionElementwise IEEE sign-bit negation.
• arm_nn_fill_f32functionFill a float32 vector with one value.
• arm_elementwise_div_f32functionElementwise float32t division: output = clamp(input1 / input2).
• arm_elementwise_div_broadcast_f32functionfloat32t division with positive, contiguous NHWC broadcasting.
• arm_elementwise_mul_f32functionElementwise multiply with optional output clamp.
• arm_minimum_f32functionElementwise minimum with TensorFlow Lite NHWC broadcasting: each dimension of the two inputs must be equal or 1, and outputdims must be their broadcast shape.
• arm_maximum_f32functionElementwise maximum with TensorFlow Lite NHWC broadcasting: each dimension of the two inputs must be equal or 1, and outputdims must be their broadcast shape.
• arm_elementwise_sub_broadcast_f32functionElementwise subtract with TensorFlow Lite NHWC broadcasting and an output clamp.
• arm_elementwise_add_broadcast_f32functionElementwise add with TensorFlow Lite NHWC broadcasting and an output clamp.
• arm_elementwise_mul_broadcast_f32functionElementwise multiply with TensorFlow Lite NHWC broadcasting and an output clamp.
• arm_nn_sqrt_f32functionElementwise square root.
• arm_rsqrt_f32functionElementwise reciprocal square root, 1 / sqrt(x).
• arm_elementwise_add_f16functionElementwise add with optional output clamp.
• arm_elementwise_add_fp16functionLegacy float16 elementwise add with fused clamp, kept only for source compatibility with callers that predate armelementwiseaddf16().
• arm_elementwise_sub_f16functionElementwise subtract with optional output clamp.
• arm_elementwise_squared_difference_f16functionElementwise squared difference of two float16 vectors.
• arm_nn_abs_f16functionElementwise absolute value.
• arm_nn_neg_f16functionElementwise IEEE sign-bit negation.
• arm_nn_fill_f16functionFill a float16 vector with one value; bit copy of value, NaN payload included.
• arm_split_f16functionSplit a float32 tensor of any rank into several tensors along one axis.
• arm_strided_slice_f16functionStrided slice for float32 data (pure copy, TensorFlow Lite compatible).
• arm_elementwise_div_f16functionElementwise float16t division: output = clamp(input1 / input2).
• arm_elementwise_div_broadcast_f16functionfloat16t division with positive, contiguous NHWC broadcasting.
• arm_elementwise_mul_f16functionElementwise multiply with optional output clamp.
• arm_minimum_f16functionElementwise minimum with TensorFlow Lite NHWC broadcasting: each dimension of the two inputs must be equal or 1, and outputdims must be their broadcast shape.
• arm_maximum_f16functionElementwise maximum with TensorFlow Lite NHWC broadcasting: each dimension of the two inputs must be equal or 1, and outputdims must be their broadcast shape.
• arm_elementwise_sub_broadcast_f16functionElementwise subtract with TensorFlow Lite NHWC broadcasting and an output clamp.
• arm_elementwise_add_broadcast_f16functionElementwise add with TensorFlow Lite NHWC broadcasting and an output clamp.
• arm_elementwise_mul_broadcast_f16functionElementwise multiply with TensorFlow Lite NHWC broadcasting and an output clamp.
• arm_nn_sqrt_f16functionElementwise square root of a float16 tensor.
• arm_rsqrt_f16functionElementwise reciprocal square root of a float16 tensor, 1 / sqrt(x).

function

arm_elementwise_add_f32

C

Elementwise add with optional output clamp.

Include/arm_nnfunctions_flt.h:1140

arm_cmsis_nn_status arm_elementwise_add_f32(
    const float32_t *input_1_vect,
    const float32_t *input_2_vect,
    float32_t *output,
    float32_t out_activation_min,
    float32_t out_activation_max,
    int32_t block_size
)

Elementwise add with optional output clamp.

NaN propagates through the clamp (TensorFlow Lite semantics): a quiet NaN in either input operand, or a NaN produced by the arithmetic itself (such as Inf + (-Inf) for add), yields a NaN at that output element. This holds at every optimization level, on the toolchains this project gates (see the Testing & Verification guide, docs/guides/verification.md), including the shipped -Ofast (CMSIS_OPTIMIZATION_LEVEL in the top-level CMakeLists.txt): the clamp classifies NaN on the integer bit pattern of the value rather than with a floating-point compare, and the -ffinite-math-only that -Ofast implies grants no license to fold integer arithmetic. Verified by host execution and by disassembly on gated Arm GNU Toolchain 14.3.Rel1 (where the unguarded form demonstrably folds) and 13.x/15.x and armclang 6.23; ATfE unexamined cross-toolchain on-target execution is #340’s scope. See issues #333 and #334. Only the NaN-ness of the element is guaranteed, not a particular NaN payload. Infinities that are not NaN still clamp to the activation bounds (and pass through unchanged under the +/-INFINITY “no clamp” idiom).

Parameters

Parameters of arm_elementwise_add_f32

Name	Type	Direction	Description
input_1_vect	const float32_t *	in	Pointer to the first input vector.
input_2_vect	const float32_t *	in	Pointer to the second input vector.
output	float32_t *	out	Pointer to the output vector.
out_activation_min	float32_t	in	Minimum output clamp value.
out_activation_max	float32_t	in	Maximum output clamp value.
block_size	int32_t	in	Number of elements to process.

Returns

Returns of arm_elementwise_add_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_elementwise_sub_f32

C

Elementwise subtract with optional output clamp.

Include/arm_nnfunctions_flt.h:1172

arm_cmsis_nn_status arm_elementwise_sub_f32(
    const float32_t *input_1_vect,
    const float32_t *input_2_vect,
    float32_t *output,
    float32_t out_activation_min,
    float32_t out_activation_max,
    int32_t block_size
)

Elementwise subtract with optional output clamp.

NaN propagates through the clamp (TensorFlow Lite semantics): a quiet NaN in either input operand, or a NaN produced by the arithmetic itself (such as Inf - Inf for subtract), yields a NaN at that output element. This holds at every optimization level, on the toolchains this project gates (see the Testing & Verification guide, docs/guides/verification.md), including the shipped -Ofast (CMSIS_OPTIMIZATION_LEVEL in the top-level CMakeLists.txt): the clamp classifies NaN on the integer bit pattern of the value rather than with a floating-point compare, and the -ffinite-math-only that -Ofast implies grants no license to fold integer arithmetic. Verified by host execution and by disassembly on gated Arm GNU Toolchain 14.3.Rel1 (where the unguarded form demonstrably folds) and 13.x/15.x and armclang 6.23; ATfE unexamined cross-toolchain on-target execution is #340’s scope. See issues #333 and #334. Only the NaN-ness of the element is guaranteed, not a particular NaN payload. Infinities that are not NaN still clamp to the activation bounds (and pass through unchanged under the +/-INFINITY “no clamp” idiom).

Parameters

Parameters of arm_elementwise_sub_f32

Name	Type	Direction	Description
input_1_vect	const float32_t *	in	Pointer to the first input vector (minuend).
input_2_vect	const float32_t *	in	Pointer to the second input vector (subtrahend).
output	float32_t *	out	Pointer to the output vector.
out_activation_min	float32_t	in	Minimum output clamp value.
out_activation_max	float32_t	in	Maximum output clamp value.
block_size	int32_t	in	Number of elements to process.

Returns

Returns of arm_elementwise_sub_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_elementwise_squared_difference_f32

C

Elementwise squared difference of contiguous FP32 vectors.

Include/arm_nnfunctions_flt.h:1210

arm_cmsis_nn_status arm_elementwise_squared_difference_f32(
    const float32_t *input_1_vect,
    const float32_t *input_2_vect,
    float32_t *output,
    int32_t block_size
)

Elementwise squared difference of contiguous FP32 vectors.

Computes (input_1 - input_2) squared, rounding the subtraction to FP32 before multiplication. No activation clamp, broadcasting or scratch is used. NaNs propagate (payload unspecified); infinite differences yield positive infinity. Overflow yields positive infinity under round-to-nearest. Scalar arithmetic follows the active floating-point controls. MVE arithmetic uses round-to-nearest and flushes FP32 subnormal operands and results regardless of FPSCR (StandardFPSCRValue); with FPSCR.FZ clear, the MVE path redoes the lanes whose square it flushed on the scalar FPU. At round-to-nearest the MVE path therefore gives the scalar path’s result with FZ set or clear, subnormal squares included; under another rounding mode only redone lanes follow it. With FZ clear, an in-place call checks every block, and a call with a separate output that meets a nonzero difference below 2^-63 makes a second, block-by-block pass. Automatic vectorization (ARM_MATH_AUTOVECTORIZE) has no redo and may mix flushed vector lanes with scalar tails; set scalar round-to-nearest and FZ=1 when consistent results are required there. Equal finite operands produce positive zero.

Buffers must be naturally aligned and hold block_size elements. Output may exactly equal either input; other partial overlaps are unsupported. Null pointers, nonpositive counts and byte counts above INT32_MAX are rejected before writing output.

Parameters

Parameters of arm_elementwise_squared_difference_f32

Name	Type	Direction	Description
input_1_vect	const float32_t *	in	First input vector.
input_2_vect	const float32_t *	in	Second input vector.
output	float32_t *	out	Output vector.
block_size	int32_t	in	Number of elements (1..INT32_MAX / sizeof(float32_t)).

Returns

Returns of arm_elementwise_squared_difference_f32

Description
ARM_CMSIS_NN_SUCCESS or ARM_CMSIS_NN_ARG_ERROR.

function

arm_nn_abs_f32

C

Elementwise absolute value.

Include/arm_nnfunctions_flt.h:1224

arm_cmsis_nn_status arm_nn_abs_f32(const float32_t *input, float32_t *output, int32_t block_size)

Elementwise absolute value.

Parameters

Parameters of arm_nn_abs_f32

Name	Type	Direction	Description
input	const float32_t *	in	Pointer to the input vector.
output	float32_t *	out	Pointer to the output vector.
block_size	int32_t	in	Number of elements to process.

Returns

Returns of arm_nn_abs_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_nn_neg_f32

C

Elementwise IEEE sign-bit negation.

Include/arm_nnfunctions_flt.h:1243

arm_cmsis_nn_status arm_nn_neg_f32(const float32_t *input, float32_t *output, int32_t count)

Elementwise IEEE sign-bit negation.

Toggles only the sign bit, preserving every other bit, including signaling/quiet NaN payloads, subnormals and infinities. Positive and negative zero exchange. No floating arithmetic or conversion is performed; FP flush/default-NaN modes do not affect the result. Exact in-place use is supported; partial overlap is not. Buffers must have natural element alignment and room for count elements. A zero count writes nothing and accepts NULL data pointers. Negative counts, byte counts above INT32_MAX, and NULL pointers for nonempty calls are rejected before any output write. No scratch is needed.

Parameters

Parameters of arm_nn_neg_f32

Name	Type	Direction	Description
input	const float32_t *	in	Input buffer.
output	float32_t *	out	Output buffer (may equal input).
count	int32_t	in	Number of elements.

Returns

Returns of arm_nn_neg_f32

Description
ARM_CMSIS_NN_SUCCESS or ARM_CMSIS_NN_ARG_ERROR.

function

arm_nn_fill_f32

C

Fill a float32 vector with one value.

Include/arm_nnfunctions_flt.h:1259

arm_cmsis_nn_status arm_nn_fill_f32(float32_t value, float32_t *output, int32_t block_size)

Fill a float32 vector with one value.

Bit copy of value into every element (vector splat / plain stores), so a NaN fill value lands bit-exact, sign and payload included. Not named arm_fill_f32: CMSIS-DSP exports that symbol.

Parameters

Parameters of arm_nn_fill_f32

Name	Type	Direction	Description
value	float32_t	in	Fill value.
output	float32_t *	out	Pointer to the output vector.
block_size	int32_t	in	Number of elements to write (0 is a no-op).

Returns

Returns of arm_nn_fill_f32

Description
`ARM_CMSIS_NN_SUCCESS`, or `ARM_CMSIS_NN_ARG_ERROR` when `block_size` is negative or `output` is NULL with a non-zero `block_size`.

function

arm_elementwise_div_f32

C

Elementwise float32t division: output = clamp(input1 / input2).

Include/arm_nnfunctions_flt.h:1280

arm_cmsis_nn_status arm_elementwise_div_f32(
    const float32_t *input_1_vect,
    const float32_t *input_2_vect,
    float32_t *output,
    float32_t out_activation_min,
    float32_t out_activation_max,
    int32_t block_size
)

Elementwise float32_t division: output = clamp(input_1 / input_2).

Note

Uses division, never a rounded reciprocal multiplication. FP32 arithmetic is used. Round-to-nearest and gradual underflow are required for reference parity. The caller owns the floating-point environment, valid storage and ordered activation bounds. NaNs propagate (payload unspecified); signed zeros and infinities follow IEEE division before clamping. Other partial overlaps are unsupported. MVE and DSP builds use scalar division. Clang/Armclang must compile the DIV source files with -fno-fast-math; both CMake manifests apply this automatically (Clang requires CMake >= 3.18). Pack/manual builds must supply that per-file option.

Parameters

Parameters of arm_elementwise_div_f32

Name	Type	Direction	Description
input_1_vect	const float32_t *	in	Numerator, block_size elements.
input_2_vect	const float32_t *	in	Denominator, block_size elements.
output	float32_t *	out	Result, block_size elements; exact in-place alias with either input is allowed.
out_activation_min	float32_t	in	Lower activation bound (not NaN).
out_activation_max	float32_t	in	Upper activation bound (not NaN, at least the lower bound).
block_size	int32_t	in	Positive element count, at most INT32_MAX / sizeof(float32_t).

Returns

Returns of arm_elementwise_div_f32

Description
ARM_CMSIS_NN_ARG_ERROR for null data or invalid count; no output writes on error.
ARM_CMSIS_NN_SUCCESS otherwise. No scratch buffer is required.

function

arm_elementwise_div_broadcast_f32

C

float32t division with positive, contiguous NHWC broadcasting.

Include/arm_nnfunctions_flt.h:1304

arm_cmsis_nn_status arm_elementwise_div_broadcast_f32(
    const float32_t *input_1_data,
    const cmsis_nn_dims *input_1_dims,
    const float32_t *input_2_data,
    const cmsis_nn_dims *input_2_dims,
    float32_t *output_data,
    const cmsis_nn_dims *output_dims,
    float32_t out_activation_min,
    float32_t out_activation_max
)

float32_t division with positive, contiguous NHWC broadcasting.

Note

No scratch or materialized broadcast is needed. Smaller ranks are left-padded with ones. Arithmetic and activation semantics match arm_elementwise_div_f32; the caller owns valid storage and ordered activation bounds. Dimension structures must remain unchanged.

Parameters

Parameters of arm_elementwise_div_broadcast_f32

Name	Type	Direction	Description
input_1_data	const float32_t *	in	Numerator tensor.
input_1_dims	const cmsis_nn_dims *	in	Numerator NHWC dimensions.
input_2_data	const float32_t *	in	Denominator tensor.
input_2_dims	const cmsis_nn_dims *	in	Denominator NHWC dimensions.
output_data	float32_t *	out	Output tensor, disjoint from both inputs and dimension structures.
output_dims	const cmsis_nn_dims *	in	Output NHWC dimensions: the maximum input extent on each axis.
out_activation_min	float32_t	in	Lower activation bound (not NaN).
out_activation_max	float32_t	in	Upper activation bound (not NaN, at least the lower bound).

Returns

Returns of arm_elementwise_div_broadcast_f32

Description
ARM_CMSIS_NN_ARG_ERROR for null pointers, nonpositive extents, incompatible shapes, or output element count exceeding INT32_MAX / sizeof(float32_t); no output writes on error.
ARM_CMSIS_NN_SUCCESS otherwise. Each pair of input extents must be equal or one must be 1.

function

arm_elementwise_mul_f32

C

Elementwise multiply with optional output clamp.

Include/arm_nnfunctions_flt.h:1338

arm_cmsis_nn_status arm_elementwise_mul_f32(
    const float32_t *input_1_vect,
    const float32_t *input_2_vect,
    float32_t *output,
    float32_t out_activation_min,
    float32_t out_activation_max,
    int32_t block_size
)

Elementwise multiply with optional output clamp.

NaN propagates through the clamp (TensorFlow Lite semantics): a quiet NaN in either input operand, or a NaN produced by the arithmetic itself (such as 0 * Inf for multiply), yields a NaN at that output element. This holds at every optimization level, on the toolchains this project gates (see the Testing & Verification guide, docs/guides/verification.md), including the shipped -Ofast (CMSIS_OPTIMIZATION_LEVEL in the top-level CMakeLists.txt): the clamp classifies NaN on the integer bit pattern of the value rather than with a floating-point compare, and the -ffinite-math-only that -Ofast implies grants no license to fold integer arithmetic. Verified by host execution and by disassembly on gated Arm GNU Toolchain 14.3.Rel1 (where the unguarded form demonstrably folds) and 13.x/15.x and armclang 6.23; ATfE unexamined cross-toolchain on-target execution is #340’s scope. See issues #333 and #334. Only the NaN-ness of the element is guaranteed, not a particular NaN payload. Infinities that are not NaN still clamp to the activation bounds (and pass through unchanged under the +/-INFINITY “no clamp” idiom).

Parameters

Parameters of arm_elementwise_mul_f32

Name	Type	Direction	Description
input_1_vect	const float32_t *	in	Pointer to the first input vector.
input_2_vect	const float32_t *	in	Pointer to the second input vector.
output	float32_t *	out	Pointer to the output vector.
out_activation_min	float32_t	in	Minimum output clamp value.
out_activation_max	float32_t	in	Maximum output clamp value.
block_size	int32_t	in	Number of elements to process.

Returns

Returns of arm_elementwise_mul_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_minimum_f32

C

Elementwise minimum with TensorFlow Lite NHWC broadcasting: each dimension of the two inputs must be equal or 1, and outputdims must be their broadcast shape.

Include/arm_nnfunctions_flt.h:1408

arm_cmsis_nn_status arm_minimum_f32(
    const cmsis_nn_context *ctx,
    const float32_t *input_1_data,
    const cmsis_nn_dims *input_1_dims,
    const float32_t *input_2_data,
    const cmsis_nn_dims *input_2_dims,
    float32_t *output_data,
    const cmsis_nn_dims *output_dims
)

Elementwise minimum with TensorFlow Lite NHWC broadcasting: each dimension of the two inputs must be equal or 1, and output_dims must be their broadcast shape.

The result for a tie between zeros of opposite sign, and for any non-finite input, is unspecified. The Helium leg is VMAXNM / VMINNM, which implement IEEE maxNum / minNum: they break a zero tie by sign - maximum returns +0.0, minimum returns -0.0 - and they suppress NaN, returning the non-NaN operand and a default quiet NaN when both operands are NaN. The scalar leg breaks the tie by operand position instead, and which position wins is not fixed either: the shipped -Ofast (CMSIS_OPTIMIZATION_LEVEL in the top-level CMakeLists.txt) implies -fno-signed-zeros and -ffinite-math-only, which license the compiler to answer a zero tie or a NaN either way, and the answer measurably differs between build targets, between optimization levels, and between the contiguous and the broadcast-scalar loop of the same build. Both zero answers compare equal to zero, so the difference is invisible to anything that is not bit-exact; a caller that cares about the sign of a zero, or about NaN, must screen its inputs rather than rely on either leg. See issue #316, and #333 for the same -ffinite-math-only caveat on the elementwise family.

Parameters

Parameters of arm_minimum_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Function context. Unused; may be NULL.
input_1_data	const float32_t *	in	Input 1, NHWC, sized by `input_1_dims`.
input_1_dims	const cmsis_nn_dims *	in	Dimensions of input 1.
input_2_data	const float32_t *	in	Input 2, NHWC, sized by `input_2_dims`.
input_2_dims	const cmsis_nn_dims *	in	Dimensions of input 2.
output_data	float32_t *	out	Output, NHWC, sized by `output_dims`.
output_dims	const cmsis_nn_dims *	in	Broadcast output dimensions.

Returns

Returns of arm_minimum_f32

Description
ARM_CMSIS_NN_SUCCESS on success, or ARM_CMSIS_NN_ARG_ERROR when a pointer is NULL, a dimension is not positive, the shapes are not broadcast-compatible, or the output shape is not their broadcast shape. `ctx` is unused and may be NULL.

function

arm_maximum_f32

C

Elementwise maximum with TensorFlow Lite NHWC broadcasting: each dimension of the two inputs must be equal or 1, and outputdims must be their broadcast shape.

Include/arm_nnfunctions_flt.h:1444

arm_cmsis_nn_status arm_maximum_f32(
    const cmsis_nn_context *ctx,
    const float32_t *input_1_data,
    const cmsis_nn_dims *input_1_dims,
    const float32_t *input_2_data,
    const cmsis_nn_dims *input_2_dims,
    float32_t *output_data,
    const cmsis_nn_dims *output_dims
)

Elementwise maximum with TensorFlow Lite NHWC broadcasting: each dimension of the two inputs must be equal or 1, and output_dims must be their broadcast shape.

The result for a tie between zeros of opposite sign, and for any non-finite input, is unspecified. The Helium leg is VMAXNM / VMINNM, which implement IEEE maxNum / minNum: they break a zero tie by sign - maximum returns +0.0, minimum returns -0.0 - and they suppress NaN, returning the non-NaN operand and a default quiet NaN when both operands are NaN. The scalar leg breaks the tie by operand position instead, and which position wins is not fixed either: the shipped -Ofast (CMSIS_OPTIMIZATION_LEVEL in the top-level CMakeLists.txt) implies -fno-signed-zeros and -ffinite-math-only, which license the compiler to answer a zero tie or a NaN either way, and the answer measurably differs between build targets, between optimization levels, and between the contiguous and the broadcast-scalar loop of the same build. Both zero answers compare equal to zero, so the difference is invisible to anything that is not bit-exact; a caller that cares about the sign of a zero, or about NaN, must screen its inputs rather than rely on either leg. See issue #316, and #333 for the same -ffinite-math-only caveat on the elementwise family.

Parameters

Parameters of arm_maximum_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Function context. Unused; may be NULL.
input_1_data	const float32_t *	in	Input 1, NHWC, sized by `input_1_dims`.
input_1_dims	const cmsis_nn_dims *	in	Dimensions of input 1.
input_2_data	const float32_t *	in	Input 2, NHWC, sized by `input_2_dims`.
input_2_dims	const cmsis_nn_dims *	in	Dimensions of input 2.
output_data	float32_t *	out	Output, NHWC, sized by `output_dims`.
output_dims	const cmsis_nn_dims *	in	Broadcast output dimensions.

Returns

Returns of arm_maximum_f32

Description
ARM_CMSIS_NN_SUCCESS on success, or ARM_CMSIS_NN_ARG_ERROR when a pointer is NULL, a dimension is not positive, the shapes are not broadcast-compatible, or the output shape is not their broadcast shape. `ctx` is unused and may be NULL.

function

arm_elementwise_sub_broadcast_f32

C

Elementwise subtract with TensorFlow Lite NHWC broadcasting and an output clamp.

Include/arm_nnfunctions_flt.h:1483

arm_cmsis_nn_status arm_elementwise_sub_broadcast_f32(
    const float32_t *input_1_data,
    const cmsis_nn_dims *input_1_dims,
    const float32_t *input_2_data,
    const cmsis_nn_dims *input_2_dims,
    float32_t *output_data,
    const cmsis_nn_dims *output_dims,
    float32_t out_activation_min,
    float32_t out_activation_max
)

Elementwise subtract with TensorFlow Lite NHWC broadcasting and an output clamp.

Broadcasting follows the NumPy / TensorFlow Lite rule per dimension: each of n, h, w and c of the two inputs must be equal or 1, a dimension of 1 is repeated along that axis, and output_dims must be the elementwise maximum of the two input shapes. A dimension of 0 or less is rejected.

Numerics are those of arm_elementwise_sub_f32 applied to the materialised broadcast operands: identical arithmetic and clamp on every path, so on the shipped Cortex-M legs (M4, M55) the output is bit-identical to that kernel, NaN payload aside, and its NaN contract holds here unchanged a NaN in either operand, or one produced by the arithmetic, propagates through the clamp at every optimization level, while non-NaN infinities clamp to the bounds. On other hosts built with -fno-signed-zeros the sign of a zero that ties with a zero clamp bound is compiler-licensed and may differ between this walk and the flat loop. The bounds must be ordered and non-NaN. When input 1 is the broadcast scalar the result is computed as scalar - element, not as the negation of element - scalar, which differs at a zero result; whether the sign of a zero survives is then subject to the same -fno-signed-zeros license the shipped -Ofast grants the compiler on the flat kernels.

Parameters

Parameters of arm_elementwise_sub_broadcast_f32

Name	Type	Direction	Description
input_1_data	const float32_t *	in	Minuend, NHWC, sized by `input_1_dims`.
input_1_dims	const cmsis_nn_dims *	in	Dimensions of input 1.
input_2_data	const float32_t *	in	Subtrahend, NHWC, sized by `input_2_dims`.
input_2_dims	const cmsis_nn_dims *	in	Dimensions of input 2.
output_data	float32_t *	out	Output, NHWC, sized by `output_dims`.
output_dims	const cmsis_nn_dims *	in	Broadcast output dimensions.
out_activation_min	float32_t	in	Minimum output clamp value.
out_activation_max	float32_t	in	Maximum output clamp value.

Returns

Returns of arm_elementwise_sub_broadcast_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success, or `ARM_CMSIS_NN_ARG_ERROR` when a pointer is NULL, a dimension is not positive, the shapes are not broadcast-compatible, or the output shape is not their broadcast shape. Nothing is written on error.

function

arm_elementwise_add_broadcast_f32

C

Elementwise add with TensorFlow Lite NHWC broadcasting and an output clamp.

Include/arm_nnfunctions_flt.h:1507

arm_cmsis_nn_status arm_elementwise_add_broadcast_f32(
    const float32_t *input_1_data,
    const cmsis_nn_dims *input_1_dims,
    const float32_t *input_2_data,
    const cmsis_nn_dims *input_2_dims,
    float32_t *output_data,
    const cmsis_nn_dims *output_dims,
    float32_t out_activation_min,
    float32_t out_activation_max
)

Elementwise add with TensorFlow Lite NHWC broadcasting and an output clamp.

Broadcast rules, argument checking and return values as for arm_elementwise_sub_broadcast_f32; numerics are those of arm_elementwise_add_f32 on the materialised broadcast operands, including its NaN contract.

Parameters

Parameters of arm_elementwise_add_broadcast_f32

Name	Type	Direction	Description
input_1_data	const float32_t *	in	First input, NHWC, sized by `input_1_dims`.
input_1_dims	const cmsis_nn_dims *	in	Dimensions of input 1.
input_2_data	const float32_t *	in	Second input, NHWC, sized by `input_2_dims`.
input_2_dims	const cmsis_nn_dims *	in	Dimensions of input 2.
output_data	float32_t *	out	Output, NHWC, sized by `output_dims`.
output_dims	const cmsis_nn_dims *	in	Broadcast output dimensions.
out_activation_min	float32_t	in	Minimum output clamp value.
out_activation_max	float32_t	in	Maximum output clamp value.

function

arm_elementwise_mul_broadcast_f32

C

Elementwise multiply with TensorFlow Lite NHWC broadcasting and an output clamp.

Include/arm_nnfunctions_flt.h:1531

arm_cmsis_nn_status arm_elementwise_mul_broadcast_f32(
    const float32_t *input_1_data,
    const cmsis_nn_dims *input_1_dims,
    const float32_t *input_2_data,
    const cmsis_nn_dims *input_2_dims,
    float32_t *output_data,
    const cmsis_nn_dims *output_dims,
    float32_t out_activation_min,
    float32_t out_activation_max
)

Elementwise multiply with TensorFlow Lite NHWC broadcasting and an output clamp.

Broadcast rules, argument checking and return values as for arm_elementwise_sub_broadcast_f32; numerics are those of arm_elementwise_mul_f32 on the materialised broadcast operands, including its NaN contract.

Parameters

Parameters of arm_elementwise_mul_broadcast_f32

Name	Type	Direction	Description
input_1_data	const float32_t *	in	First input, NHWC, sized by `input_1_dims`.
input_1_dims	const cmsis_nn_dims *	in	Dimensions of input 1.
input_2_data	const float32_t *	in	Second input, NHWC, sized by `input_2_dims`.
input_2_dims	const cmsis_nn_dims *	in	Dimensions of input 2.
output_data	float32_t *	out	Output, NHWC, sized by `output_dims`.
output_dims	const cmsis_nn_dims *	in	Broadcast output dimensions.
out_activation_min	float32_t	in	Minimum output clamp value.
out_activation_max	float32_t	in	Maximum output clamp value.

function

arm_nn_sqrt_f32

C

Elementwise square root.

Include/arm_nnfunctions_flt.h:1562

arm_cmsis_nn_status arm_nn_sqrt_f32(const float32_t *input, float32_t *output, int32_t block_size)

Elementwise square root.

The value path is scalar on every toolchain, because Helium has no vector square root. armclang and ATfE do vectorize the surrounding special-value classification; the results are bit-identical to the GCC scalar build, verified by executing both toolchains’ objects (#295). Normal positive inputs evaluate sqrtf(x), which IEEE 754 makes correctly rounded, so results are bit-exact to a float64 reference. Subnormal inputs follow FPSCR.FZ: where flush-to-zero is set - the Corstone-300 FVP default, and any host binary linked at -Ofast, where crtfastmath sets DAZ and FTZ - a subnormal input reads as zero and the result is +0. The float16 pair is immune, because it widens to a normal float32 first. Special values are decided on the bit pattern and returned as literals, independent of -ffinite-math-only and FPSCR.DN: +0 -> +0, -0 -> -0, +Inf -> +Inf, negative (including -Inf) -> quiet NaN 0x7FC00000, NaN -> the same NaN with the quiet bit set (sign and payload kept).

Parameters

Parameters of arm_nn_sqrt_f32

Name	Type	Direction	Description
input	const float32_t *	in	Pointer to the input vector.
output	float32_t *	out	Pointer to the output vector; may alias `input`.
block_size	int32_t	in	Number of elements to process.

Returns

Returns of arm_nn_sqrt_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_rsqrt_f32

C

Elementwise reciprocal square root, 1 / sqrt(x).

Include/arm_nnfunctions_flt.h:1581

arm_cmsis_nn_status arm_rsqrt_f32(const float32_t *input, float32_t *output, int32_t block_size)

Elementwise reciprocal square root, 1 / sqrt(x).

Same value path as arm_nn_sqrt_f32, including its FPSCR.FZ behaviour on subnormal inputs, where the result is +Inf. Normal positive inputs evaluate 1.0f / sqrtf(x) in float32: two IEEE roundings, so the result is within 1 ulp of the correctly rounded value (measured against a float64 reference; x = 4^k is exact). Special values are decided on the bit pattern and returned as literals: +0 -> +Inf, -0 -> -Inf, +Inf -> +0, negative (including -Inf) -> quiet NaN 0x7FC00000, NaN -> the same NaN with the quiet bit set (sign and payload kept).

Parameters

Parameters of arm_rsqrt_f32

Name	Type	Direction	Description
input	const float32_t *	in	Pointer to the input vector.
output	float32_t *	out	Pointer to the output vector; may alias `input`.
block_size	int32_t	in	Number of elements to process.

Returns

Returns of arm_rsqrt_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_elementwise_add_f16

C

Elementwise add with optional output clamp.

Include/arm_nnfunctions_flt.h:4071

arm_cmsis_nn_status arm_elementwise_add_f16(
    const float16_t *input_1_vect,
    const float16_t *input_2_vect,
    float16_t *output,
    float16_t out_activation_min,
    float16_t out_activation_max,
    int32_t block_size
)

Elementwise add with optional output clamp.

NaN propagates through the clamp (TensorFlow Lite semantics): a quiet NaN in either input operand, or a NaN produced by the arithmetic itself (such as Inf + (-Inf) for add), yields a NaN at that output element. This holds at every optimization level, on the toolchains this project gates (see the Testing & Verification guide, docs/guides/verification.md), including the shipped -Ofast (CMSIS_OPTIMIZATION_LEVEL in the top-level CMakeLists.txt): the clamp classifies NaN on the integer bit pattern of the value rather than with a floating-point compare, and the -ffinite-math-only that -Ofast implies grants no license to fold integer arithmetic. Verified by host execution and by disassembly on gated Arm GNU Toolchain 14.3.Rel1 (where the unguarded form demonstrably folds) and 13.x/15.x and armclang 6.23; ATfE unexamined cross-toolchain on-target execution is #340’s scope. See issues #333 and #334. Only the NaN-ness of the element is guaranteed, not a particular NaN payload. Infinities that are not NaN still clamp to the activation bounds (and pass through unchanged under the +/-INFINITY “no clamp” idiom).

Parameters

Parameters of arm_elementwise_add_f16

Name	Type	Direction	Description
input_1_vect	const float16_t *	in	Pointer to the first input vector.
input_2_vect	const float16_t *	in	Pointer to the second input vector.
output	float16_t *	out	Pointer to the output vector.
out_activation_min	float16_t	in	Minimum output clamp value.
out_activation_max	float16_t	in	Maximum output clamp value.
block_size	int32_t	in	Number of elements to process.

Returns

Returns of arm_elementwise_add_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_elementwise_add_fp16

C

Legacy float16 elementwise add with fused clamp, kept only for source compatibility with callers that predate armelementwiseaddf16().

Include/arm_nnfunctions_flt.h:4102

arm_cmsis_nn_status arm_elementwise_add_fp16(
    const float16_t *input_1_vect,
    const float16_t *input_2_vect,
    float16_t *output,
    const float16_t out_activation_min,
    const float16_t out_activation_max,
    const int32_t block_size
)

Legacy float16 elementwise add with fused clamp, kept only for source compatibility with callers that predate arm_elementwise_add_f16(). New code should call arm_elementwise_add_f16() instead.

This entry does NOT share the contract of arm_elementwise_add_f16():

Caution

No argument validation is performed. A NULL input_1_vect, input_2_vect or output is dereferenced rather than reported. A block_size of 0 writes nothing and still returns ARM_CMSIS_NN_SUCCESS, where arm_elementwise_add_f16() returns ARM_CMSIS_NN_ARG_ERROR.

Note

The clamp does not propagate NaN. Both the Helium path (vminnm/vmaxnm) and the scalar path (the non-propagating MIN/MAX clamp helper) bound against out_activation_max first, so a NaN produced by the addition comes back as out_activation_max. arm_elementwise_add_f16() documents TensorFlow Lite NaN propagation; this entry does not implement it.

Parameters

Parameters of arm_elementwise_add_fp16

Name	Type	Direction	Description
input_1_vect	const float16_t *	in	Pointer to the first input vector. Must not be NULL.
input_2_vect	const float16_t *	in	Pointer to the second input vector. Must not be NULL.
output	float16_t *	out	Pointer to the output vector. Must not be NULL.
out_activation_min	const float16_t	in	Minimum output clamp value.
out_activation_max	const float16_t	in	Maximum output clamp value.
block_size	const int32_t	in	Number of elements to process.

Returns

Returns of arm_elementwise_add_fp16

Description
`ARM_CMSIS_NN_SUCCESS` unconditionally.

function

arm_elementwise_sub_f16

C

Elementwise subtract with optional output clamp.

Include/arm_nnfunctions_flt.h:4112

arm_cmsis_nn_status arm_elementwise_sub_f16(
    const float16_t *input_1_vect,
    const float16_t *input_2_vect,
    float16_t *output,
    float16_t out_activation_min,
    float16_t out_activation_max,
    int32_t block_size
)

Elementwise subtract with optional output clamp.

NaN propagates through the clamp (TensorFlow Lite semantics): a quiet NaN in either input operand, or a NaN produced by the arithmetic itself (such as Inf - Inf for subtract), yields a NaN at that output element. This holds at every optimization level, on the toolchains this project gates (see the Testing & Verification guide, docs/guides/verification.md), including the shipped -Ofast (CMSIS_OPTIMIZATION_LEVEL in the top-level CMakeLists.txt): the clamp classifies NaN on the integer bit pattern of the value rather than with a floating-point compare, and the -ffinite-math-only that -Ofast implies grants no license to fold integer arithmetic. Verified by host execution and by disassembly on gated Arm GNU Toolchain 14.3.Rel1 (where the unguarded form demonstrably folds) and 13.x/15.x and armclang 6.23; ATfE unexamined cross-toolchain on-target execution is #340’s scope. See issues #333 and #334. Only the NaN-ness of the element is guaranteed, not a particular NaN payload. Infinities that are not NaN still clamp to the activation bounds (and pass through unchanged under the +/-INFINITY “no clamp” idiom).

Parameters

Parameters of arm_elementwise_sub_f16

Name	Type	Direction	Description
input_1_vect	const float16_t *	in	Pointer to the first input vector (minuend).
input_2_vect	const float16_t *	in	Pointer to the second input vector (subtrahend).
output	float16_t *	out	Pointer to the output vector.
out_activation_min	float16_t	in	Minimum output clamp value.
out_activation_max	float16_t	in	Maximum output clamp value.
block_size	int32_t	in	Number of elements to process.

Returns

Returns of arm_elementwise_sub_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_elementwise_squared_difference_f16

C

Elementwise squared difference of two float16 vectors.

Include/arm_nnfunctions_flt.h:4132

arm_cmsis_nn_status arm_elementwise_squared_difference_f16(
    const float16_t *input_1_vect,
    const float16_t *input_2_vect,
    float16_t *output,
    int32_t block_size
)

Elementwise squared difference of two float16 vectors.

Each output element is calculated as (input_1_vect[i] - input_2_vect[i])^2.

Parameters

Parameters of arm_elementwise_squared_difference_f16

Name	Type	Direction	Description
input_1_vect	const float16_t *	in	Pointer to the first input vector.
input_2_vect	const float16_t *	in	Pointer to the second input vector.
output	float16_t *	out	Pointer to the output vector.
block_size	int32_t	in	Number of elements to process.

Returns

Returns of arm_elementwise_squared_difference_f16

Description
`ARM_CMSIS_NN_SUCCESS`, or `ARM_CMSIS_NN_ARG_ERROR` when an input/output pointer is NULL or `block_size` is less than 1.

function

arm_nn_abs_f16

C

Elementwise absolute value.

Include/arm_nnfunctions_flt.h:4140

arm_cmsis_nn_status arm_nn_abs_f16(const float16_t *input, float16_t *output, int32_t block_size)

Elementwise absolute value.

Parameters

Parameters of arm_nn_abs_f16

Name	Type	Direction	Description
input	const float16_t *	in	Pointer to the input vector.
output	float16_t *	out	Pointer to the output vector.
block_size	int32_t	in	Number of elements to process.

Returns

Returns of arm_nn_abs_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_nn_neg_f16

C

Elementwise IEEE sign-bit negation.

Include/arm_nnfunctions_flt.h:4143

arm_cmsis_nn_status arm_nn_neg_f16(const float16_t *input, float16_t *output, int32_t count)

Elementwise IEEE sign-bit negation.

Toggles only the sign bit, preserving every other bit, including signaling/quiet NaN payloads, subnormals and infinities. Positive and negative zero exchange. No floating arithmetic or conversion is performed; FP flush/default-NaN modes do not affect the result. Exact in-place use is supported; partial overlap is not. Buffers must have natural element alignment and room for count elements. A zero count writes nothing and accepts NULL data pointers. Negative counts, byte counts above INT32_MAX, and NULL pointers for nonempty calls are rejected before any output write. No scratch is needed.

Parameters

Parameters of arm_nn_neg_f16

Name	Type	Direction	Description
input	const float16_t *	in	Input buffer.
output	float16_t *	out	Output buffer (may equal input).
count	int32_t	in	Number of elements.

Returns

Returns of arm_nn_neg_f16

Description
ARM_CMSIS_NN_SUCCESS or ARM_CMSIS_NN_ARG_ERROR.

function

arm_nn_fill_f16

C

Fill a float16 vector with one value; bit copy of value, NaN payload included.

Include/arm_nnfunctions_flt.h:4155

arm_cmsis_nn_status arm_nn_fill_f16(float16_t value, float16_t *output, int32_t block_size)

Fill a float16 vector with one value; bit copy of value, NaN payload included.

Parameters

Parameters of arm_nn_fill_f16

Name	Type	Direction	Description
value	float16_t	in	Fill value.
output	float16_t *	out	Pointer to the output vector.
block_size	int32_t	in	Number of elements to write (0 is a no-op).

Returns

Returns of arm_nn_fill_f16

Description
`ARM_CMSIS_NN_SUCCESS`, or `ARM_CMSIS_NN_ARG_ERROR` when `block_size` is negative or `output` is NULL with a non-zero `block_size`.

function

arm_split_f16

C

Split a float32 tensor of any rank into several tensors along one axis.

Include/arm_nnfunctions_flt.h:4179

arm_cmsis_nn_status arm_split_f16(
    const float16_t *input_data,
    const int32_t input_dims,
    const int32_t *input_shape,
    const int32_t axis,
    const int32_t num_splits,
    const int32_t *split_dims,
    float16_t *const *output_data
)

Split a float32 tensor of any rank into several tensors along one axis.

Inverse of arm_concatenation_f32; per-split lengths also cover SPLIT_V. Output s has the input shape with input_shape[axis] replaced by split_dims[s]. Bit copy, NaN/Inf/-0/subnormal payloads preserved. Outputs must not overlap the input. A dimension of 0 is accepted and copies nothing.

Parameters

Parameters of arm_split_f16

Name	Type	Direction	Description
input_data	const float16_t *	in	Pointer to the flattened (row-major) input.
input_dims	const int32_t	in	Number of dimensions in `input_shape` (>= 1).
input_shape	const int32_t *	in	Input shape; `input_shape`[axis] must equal the sum of `split_dims`.
axis	const int32_t	in	Axis to split along (0 <= axis < input_dims).
num_splits	const int32_t	in	Number of outputs (>= 1).
split_dims	const int32_t *	in	Array of length `num_splits:` each output's extent along `axis`.
output_data	float16_t *const *	out	Array of `num_splits` pointers to the flattened outputs.

Returns

Returns of arm_split_f16

Description
`ARM_CMSIS_NN_SUCCESS`, or `ARM_CMSIS_NN_ARG_ERROR` (outputs untouched) on an invalid rank, axis, shape entry, split entry, split sum, NULL pointer or an element count above INT32_MAX.

function

arm_strided_slice_f16

C

Strided slice for float32 data (pure copy, TensorFlow Lite compatible).

Include/arm_nnfunctions_flt.h:4190

arm_cmsis_nn_status arm_strided_slice_f16(
    const float16_t *input_data,
    float16_t *output_data,
    const cmsis_nn_dims *const input_dims,
    const cmsis_nn_dims *const begin_dims,
    const cmsis_nn_dims *const stride_dims,
    const cmsis_nn_dims *const output_dims
)

Strided slice for float32 data (pure copy, TensorFlow Lite compatible).

Reads element i of input axis a at begin_dims[a] + i * stride_dims[a], for i from 0 to output_dims[a] - 1, and writes the elements contiguously in N, H, W, C order: output_dims->n * h * w * c elements in all. Every argument is per input axis, in input axis order [N, H, W, C], after the caller pads a lower-rank slice to 4-D.

output_dims holds the number of elements to read on each input axis. That is the output tensor’s shape only when no axis is removed: for an axis that TFLite’s shrink_axis_mask removes, or any slice whose output rank is below the input rank, pass 1 at that axis’s position, not the output tensor’s shape padded to 4-D. TFLM’s strided_slice::StridedSliceStartForAxis() and StridedSliceEndForAxis() give the per-axis begin and end the counts follow from. Example: input [2, 3, 4] sliced x[:, 1, :] (shrink axis 1) is input_dims {1, 2, 3, 4}, begin_dims {0, 0, 1, 0}, stride_dims {1, 1, 1, 1} and output_dims {1, 2, 1, 4}; the output tensor’s padded shape {1, 1, 2, 4} would read rows 1 and 2 of batch 0 instead, and still return ARM_CMSIS_NN_SUCCESS.

Every visited index must lie inside input_dims, and the output buffer must hold the elements read; neither is checked. An empty slice (a count of 0 on some axis) is rejected, so the caller skips it before the call.

Parameters

Parameters of arm_strided_slice_f16

Name	Type	Direction	Description
input_data	const float16_t *	in	Pointer to input tensor.
output_data	float16_t *	out	Pointer to output tensor.
input_dims	const cmsis_nn_dims *const	in	Input tensor dimensions, each at least 1.
begin_dims	const cmsis_nn_dims *const	in	Index of the first element read on each input axis.
stride_dims	const cmsis_nn_dims *const	in	Step between elements read on each input axis, nonzero; negative walks backwards.
output_dims	const cmsis_nn_dims *const	in	Number of elements to read on each input axis, each at least 1 (see above).

Returns

Returns of arm_strided_slice_f16

Description
ARM_CMSIS_NN_SUCCESS, or ARM_CMSIS_NN_ARG_ERROR when a pointer is NULL, an input_dims or output_dims value is less than 1, or a stride_dims value is 0.

function

arm_elementwise_div_f16

C

Elementwise float16t division: output = clamp(input1 / input2).

Include/arm_nnfunctions_flt.h:4216

arm_cmsis_nn_status arm_elementwise_div_f16(
    const float16_t *input_1_vect,
    const float16_t *input_2_vect,
    float16_t *output,
    float16_t out_activation_min,
    float16_t out_activation_max,
    int32_t block_size
)

Elementwise float16_t division: output = clamp(input_1 / input_2).

Note

Uses division, never a rounded reciprocal multiplication. FP16 operands are widened to FP32, divided, then rounded to FP16 before clamping. Round-to-nearest and gradual underflow are required for reference parity. The caller owns the floating-point environment, valid storage and ordered activation bounds. NaNs propagate (payload unspecified); signed zeros and infinities follow IEEE division before clamping. Other partial overlaps are unsupported. MVE and DSP builds use scalar division. Clang/Armclang must compile the DIV source files with -fno-fast-math; both CMake manifests apply this automatically (Clang requires CMake >= 3.18). Pack/manual builds must supply that per-file option.

Parameters

Parameters of arm_elementwise_div_f16

Name	Type	Direction	Description
input_1_vect	const float16_t *	in	Numerator, block_size elements.
input_2_vect	const float16_t *	in	Denominator, block_size elements.
output	float16_t *	out	Result, block_size elements; exact in-place alias with either input is allowed.
out_activation_min	float16_t	in	Lower activation bound (not NaN).
out_activation_max	float16_t	in	Upper activation bound (not NaN, at least the lower bound).
block_size	int32_t	in	Positive element count, at most INT32_MAX / sizeof(float16_t).

Returns

Returns of arm_elementwise_div_f16

Description
ARM_CMSIS_NN_ARG_ERROR for null data or invalid count; no output writes on error.
ARM_CMSIS_NN_SUCCESS otherwise. No scratch buffer is required.

function

arm_elementwise_div_broadcast_f16

C

float16t division with positive, contiguous NHWC broadcasting.

Include/arm_nnfunctions_flt.h:4240

arm_cmsis_nn_status arm_elementwise_div_broadcast_f16(
    const float16_t *input_1_data,
    const cmsis_nn_dims *input_1_dims,
    const float16_t *input_2_data,
    const cmsis_nn_dims *input_2_dims,
    float16_t *output_data,
    const cmsis_nn_dims *output_dims,
    float16_t out_activation_min,
    float16_t out_activation_max
)

float16_t division with positive, contiguous NHWC broadcasting.

Note

No scratch or materialized broadcast is needed. Smaller ranks are left-padded with ones. Arithmetic and activation semantics match arm_elementwise_div_f16; the caller owns valid storage and ordered activation bounds. Dimension structures must remain unchanged.

Parameters

Parameters of arm_elementwise_div_broadcast_f16

Name	Type	Direction	Description
input_1_data	const float16_t *	in	Numerator tensor.
input_1_dims	const cmsis_nn_dims *	in	Numerator NHWC dimensions.
input_2_data	const float16_t *	in	Denominator tensor.
input_2_dims	const cmsis_nn_dims *	in	Denominator NHWC dimensions.
output_data	float16_t *	out	Output tensor, disjoint from both inputs and dimension structures.
output_dims	const cmsis_nn_dims *	in	Output NHWC dimensions: the maximum input extent on each axis.
out_activation_min	float16_t	in	Lower activation bound (not NaN).
out_activation_max	float16_t	in	Upper activation bound (not NaN, at least the lower bound).

Returns

Returns of arm_elementwise_div_broadcast_f16

Description
ARM_CMSIS_NN_ARG_ERROR for null pointers, nonpositive extents, incompatible shapes, or output element count exceeding INT32_MAX / sizeof(float16_t); no output writes on error.
ARM_CMSIS_NN_SUCCESS otherwise. Each pair of input extents must be equal or one must be 1.

function

arm_elementwise_mul_f16

C

Elementwise multiply with optional output clamp.

Include/arm_nnfunctions_flt.h:4252

arm_cmsis_nn_status arm_elementwise_mul_f16(
    const float16_t *input_1_vect,
    const float16_t *input_2_vect,
    float16_t *output,
    float16_t out_activation_min,
    float16_t out_activation_max,
    int32_t block_size
)

Elementwise multiply with optional output clamp.

NaN propagates through the clamp (TensorFlow Lite semantics): a quiet NaN in either input operand, or a NaN produced by the arithmetic itself (such as 0 * Inf for multiply), yields a NaN at that output element. This holds at every optimization level, on the toolchains this project gates (see the Testing & Verification guide, docs/guides/verification.md), including the shipped -Ofast (CMSIS_OPTIMIZATION_LEVEL in the top-level CMakeLists.txt): the clamp classifies NaN on the integer bit pattern of the value rather than with a floating-point compare, and the -ffinite-math-only that -Ofast implies grants no license to fold integer arithmetic. Verified by host execution and by disassembly on gated Arm GNU Toolchain 14.3.Rel1 (where the unguarded form demonstrably folds) and 13.x/15.x and armclang 6.23; ATfE unexamined cross-toolchain on-target execution is #340’s scope. See issues #333 and #334. Only the NaN-ness of the element is guaranteed, not a particular NaN payload. Infinities that are not NaN still clamp to the activation bounds (and pass through unchanged under the +/-INFINITY “no clamp” idiom).

Parameters

Parameters of arm_elementwise_mul_f16

Name	Type	Direction	Description
input_1_vect	const float16_t *	in	Pointer to the first input vector.
input_2_vect	const float16_t *	in	Pointer to the second input vector.
output	float16_t *	out	Pointer to the output vector.
out_activation_min	float16_t	in	Minimum output clamp value.
out_activation_max	float16_t	in	Maximum output clamp value.
block_size	int32_t	in	Number of elements to process.

Returns

Returns of arm_elementwise_mul_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_minimum_f16

C

Elementwise minimum with TensorFlow Lite NHWC broadcasting: each dimension of the two inputs must be equal or 1, and outputdims must be their broadcast shape.

Include/arm_nnfunctions_flt.h:4262

arm_cmsis_nn_status arm_minimum_f16(
    const cmsis_nn_context *ctx,
    const float16_t *input_1_data,
    const cmsis_nn_dims *input_1_dims,
    const float16_t *input_2_data,
    const cmsis_nn_dims *input_2_dims,
    float16_t *output_data,
    const cmsis_nn_dims *output_dims
)

Elementwise minimum with TensorFlow Lite NHWC broadcasting: each dimension of the two inputs must be equal or 1, and output_dims must be their broadcast shape.

The result for a tie between zeros of opposite sign, and for any non-finite input, is unspecified. The Helium leg is VMAXNM / VMINNM, which implement IEEE maxNum / minNum: they break a zero tie by sign - maximum returns +0.0, minimum returns -0.0 - and they suppress NaN, returning the non-NaN operand and a default quiet NaN when both operands are NaN. The scalar leg breaks the tie by operand position instead, and which position wins is not fixed either: the shipped -Ofast (CMSIS_OPTIMIZATION_LEVEL in the top-level CMakeLists.txt) implies -fno-signed-zeros and -ffinite-math-only, which license the compiler to answer a zero tie or a NaN either way, and the answer measurably differs between build targets, between optimization levels, and between the contiguous and the broadcast-scalar loop of the same build. Both zero answers compare equal to zero, so the difference is invisible to anything that is not bit-exact; a caller that cares about the sign of a zero, or about NaN, must screen its inputs rather than rely on either leg. See issue #316, and #333 for the same -ffinite-math-only caveat on the elementwise family.

Parameters

Parameters of arm_minimum_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Function context. Unused; may be NULL.
input_1_data	const float16_t *	in	Input 1, NHWC, sized by `input_1_dims`.
input_1_dims	const cmsis_nn_dims *	in	Dimensions of input 1.
input_2_data	const float16_t *	in	Input 2, NHWC, sized by `input_2_dims`.
input_2_dims	const cmsis_nn_dims *	in	Dimensions of input 2.
output_data	float16_t *	out	Output, NHWC, sized by `output_dims`.
output_dims	const cmsis_nn_dims *	in	Broadcast output dimensions.

Returns

Returns of arm_minimum_f16

Description
ARM_CMSIS_NN_SUCCESS on success, or ARM_CMSIS_NN_ARG_ERROR when a pointer is NULL, a dimension is not positive, the shapes are not broadcast-compatible, or the output shape is not their broadcast shape. `ctx` is unused and may be NULL.

function

arm_maximum_f16

C

Elementwise maximum with TensorFlow Lite NHWC broadcasting: each dimension of the two inputs must be equal or 1, and outputdims must be their broadcast shape.

Include/arm_nnfunctions_flt.h:4273

arm_cmsis_nn_status arm_maximum_f16(
    const cmsis_nn_context *ctx,
    const float16_t *input_1_data,
    const cmsis_nn_dims *input_1_dims,
    const float16_t *input_2_data,
    const cmsis_nn_dims *input_2_dims,
    float16_t *output_data,
    const cmsis_nn_dims *output_dims
)

Elementwise maximum with TensorFlow Lite NHWC broadcasting: each dimension of the two inputs must be equal or 1, and output_dims must be their broadcast shape.

The result for a tie between zeros of opposite sign, and for any non-finite input, is unspecified. The Helium leg is VMAXNM / VMINNM, which implement IEEE maxNum / minNum: they break a zero tie by sign - maximum returns +0.0, minimum returns -0.0 - and they suppress NaN, returning the non-NaN operand and a default quiet NaN when both operands are NaN. The scalar leg breaks the tie by operand position instead, and which position wins is not fixed either: the shipped -Ofast (CMSIS_OPTIMIZATION_LEVEL in the top-level CMakeLists.txt) implies -fno-signed-zeros and -ffinite-math-only, which license the compiler to answer a zero tie or a NaN either way, and the answer measurably differs between build targets, between optimization levels, and between the contiguous and the broadcast-scalar loop of the same build. Both zero answers compare equal to zero, so the difference is invisible to anything that is not bit-exact; a caller that cares about the sign of a zero, or about NaN, must screen its inputs rather than rely on either leg. See issue #316, and #333 for the same -ffinite-math-only caveat on the elementwise family.

Parameters

Parameters of arm_maximum_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Function context. Unused; may be NULL.
input_1_data	const float16_t *	in	Input 1, NHWC, sized by `input_1_dims`.
input_1_dims	const cmsis_nn_dims *	in	Dimensions of input 1.
input_2_data	const float16_t *	in	Input 2, NHWC, sized by `input_2_dims`.
input_2_dims	const cmsis_nn_dims *	in	Dimensions of input 2.
output_data	float16_t *	out	Output, NHWC, sized by `output_dims`.
output_dims	const cmsis_nn_dims *	in	Broadcast output dimensions.

Returns

Returns of arm_maximum_f16

Description
ARM_CMSIS_NN_SUCCESS on success, or ARM_CMSIS_NN_ARG_ERROR when a pointer is NULL, a dimension is not positive, the shapes are not broadcast-compatible, or the output shape is not their broadcast shape. `ctx` is unused and may be NULL.

function

arm_elementwise_sub_broadcast_f16

C

Elementwise subtract with TensorFlow Lite NHWC broadcasting and an output clamp.

Include/arm_nnfunctions_flt.h:4286

arm_cmsis_nn_status arm_elementwise_sub_broadcast_f16(
    const float16_t *input_1_data,
    const cmsis_nn_dims *input_1_dims,
    const float16_t *input_2_data,
    const cmsis_nn_dims *input_2_dims,
    float16_t *output_data,
    const cmsis_nn_dims *output_dims,
    float16_t out_activation_min,
    float16_t out_activation_max
)

Elementwise subtract with TensorFlow Lite NHWC broadcasting and an output clamp.

Broadcasting follows the NumPy / TensorFlow Lite rule per dimension: each of n, h, w and c of the two inputs must be equal or 1, a dimension of 1 is repeated along that axis, and output_dims must be the elementwise maximum of the two input shapes. A dimension of 0 or less is rejected.

Numerics are those of arm_elementwise_sub_f32 applied to the materialised broadcast operands: identical arithmetic and clamp on every path, so on the shipped Cortex-M legs (M4, M55) the output is bit-identical to that kernel, NaN payload aside, and its NaN contract holds here unchanged a NaN in either operand, or one produced by the arithmetic, propagates through the clamp at every optimization level, while non-NaN infinities clamp to the bounds. On other hosts built with -fno-signed-zeros the sign of a zero that ties with a zero clamp bound is compiler-licensed and may differ between this walk and the flat loop. The bounds must be ordered and non-NaN. When input 1 is the broadcast scalar the result is computed as scalar - element, not as the negation of element - scalar, which differs at a zero result; whether the sign of a zero survives is then subject to the same -fno-signed-zeros license the shipped -Ofast grants the compiler on the flat kernels.

Half-precision twin: the numerics are those of arm_elementwise_sub_f16 on the materialised operands.

Parameters

Parameters of arm_elementwise_sub_broadcast_f16

Name	Type	Direction	Description
input_1_data	const float16_t *	in	Minuend, NHWC, sized by `input_1_dims`.
input_1_dims	const cmsis_nn_dims *	in	Dimensions of input 1.
input_2_data	const float16_t *	in	Subtrahend, NHWC, sized by `input_2_dims`.
input_2_dims	const cmsis_nn_dims *	in	Dimensions of input 2.
output_data	float16_t *	out	Output, NHWC, sized by `output_dims`.
output_dims	const cmsis_nn_dims *	in	Broadcast output dimensions.
out_activation_min	float16_t	in	Minimum output clamp value.
out_activation_max	float16_t	in	Maximum output clamp value.

Returns

Returns of arm_elementwise_sub_broadcast_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success, or `ARM_CMSIS_NN_ARG_ERROR` when a pointer is NULL, a dimension is not positive, the shapes are not broadcast-compatible, or the output shape is not their broadcast shape. Nothing is written on error.

function

arm_elementwise_add_broadcast_f16

C

Elementwise add with TensorFlow Lite NHWC broadcasting and an output clamp.

Include/arm_nnfunctions_flt.h:4300

arm_cmsis_nn_status arm_elementwise_add_broadcast_f16(
    const float16_t *input_1_data,
    const cmsis_nn_dims *input_1_dims,
    const float16_t *input_2_data,
    const cmsis_nn_dims *input_2_dims,
    float16_t *output_data,
    const cmsis_nn_dims *output_dims,
    float16_t out_activation_min,
    float16_t out_activation_max
)

Elementwise add with TensorFlow Lite NHWC broadcasting and an output clamp.

Broadcast rules, argument checking and return values as for arm_elementwise_sub_broadcast_f32; numerics are those of arm_elementwise_add_f32 on the materialised broadcast operands, including its NaN contract.

Half-precision twin: the numerics are those of arm_elementwise_add_f16 on the materialised operands.

Parameters

Parameters of arm_elementwise_add_broadcast_f16

Name	Type	Direction	Description
input_1_data	const float16_t *	in	First input, NHWC, sized by `input_1_dims`.
input_1_dims	const cmsis_nn_dims *	in	Dimensions of input 1.
input_2_data	const float16_t *	in	Second input, NHWC, sized by `input_2_dims`.
input_2_dims	const cmsis_nn_dims *	in	Dimensions of input 2.
output_data	float16_t *	out	Output, NHWC, sized by `output_dims`.
output_dims	const cmsis_nn_dims *	in	Broadcast output dimensions.
out_activation_min	float16_t	in	Minimum output clamp value.
out_activation_max	float16_t	in	Maximum output clamp value.

function

arm_elementwise_mul_broadcast_f16

C

Elementwise multiply with TensorFlow Lite NHWC broadcasting and an output clamp.

Include/arm_nnfunctions_flt.h:4314

arm_cmsis_nn_status arm_elementwise_mul_broadcast_f16(
    const float16_t *input_1_data,
    const cmsis_nn_dims *input_1_dims,
    const float16_t *input_2_data,
    const cmsis_nn_dims *input_2_dims,
    float16_t *output_data,
    const cmsis_nn_dims *output_dims,
    float16_t out_activation_min,
    float16_t out_activation_max
)

Elementwise multiply with TensorFlow Lite NHWC broadcasting and an output clamp.

Broadcast rules, argument checking and return values as for arm_elementwise_sub_broadcast_f32; numerics are those of arm_elementwise_mul_f32 on the materialised broadcast operands, including its NaN contract.

Half-precision twin: the numerics are those of arm_elementwise_mul_f16 on the materialised operands.

Parameters

Parameters of arm_elementwise_mul_broadcast_f16

Name	Type	Direction	Description
input_1_data	const float16_t *	in	First input, NHWC, sized by `input_1_dims`.
input_1_dims	const cmsis_nn_dims *	in	Dimensions of input 1.
input_2_data	const float16_t *	in	Second input, NHWC, sized by `input_2_dims`.
input_2_dims	const cmsis_nn_dims *	in	Dimensions of input 2.
output_data	float16_t *	out	Output, NHWC, sized by `output_dims`.
output_dims	const cmsis_nn_dims *	in	Broadcast output dimensions.
out_activation_min	float16_t	in	Minimum output clamp value.
out_activation_max	float16_t	in	Maximum output clamp value.

function

arm_nn_sqrt_f16

C

Elementwise square root of a float16 tensor.

Include/arm_nnfunctions_flt.h:4344

arm_cmsis_nn_status arm_nn_sqrt_f16(const float16_t *input, float16_t *output, int32_t block_size)

Elementwise square root of a float16 tensor.

The value path is scalar on every toolchain, because Helium has no vector square root; armclang and ATfE vectorize the surrounding classification into an MVE loop and produce bit-identical results, verified by executing their objects (#295). Each element is widened to float32, sqrtf is evaluated there and the result is rounded once to float16. Verified exhaustively: for every positive finite float16 input, subnormals included, the result is the correctly rounded float16 of the float64 square root (0 ulp, #295). Widening first also makes this pair immune to FPSCR.FZ, which flushes float32 subnormals in the f32 pair. Special values are decided on the bit pattern and returned as literals, independent of -ffinite-math-only and FPSCR.DN: +0 -> +0, -0 -> -0, +Inf -> +Inf, negative (including -Inf) -> quiet NaN 0x7E00, NaN -> the same NaN with the quiet bit set (sign and payload kept).

Parameters

Parameters of arm_nn_sqrt_f16

Name	Type	Direction	Description
input	const float16_t *	in	Pointer to the input tensor.
output	float16_t *	out	Pointer to the output tensor; may alias `input`.
block_size	int32_t	in	Number of tensor elements.

Returns

Returns of arm_nn_sqrt_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_rsqrt_f16

C

Elementwise reciprocal square root of a float16 tensor, 1 / sqrt(x).

Include/arm_nnfunctions_flt.h:4363

arm_cmsis_nn_status arm_rsqrt_f16(const float16_t *input, float16_t *output, int32_t block_size)

Elementwise reciprocal square root of a float16 tensor, 1 / sqrt(x).

Same value path as arm_nn_sqrt_f16: widen to float32, evaluate 1.0f / sqrtf(x) there, round once to float16, and so also immune to FPSCR.FZ. Verified exhaustively: for every positive finite float16 input, subnormals included, the result is the correctly rounded float16 of the float64 reciprocal square root (0 ulp, #295). Special values are decided on the bit pattern and returned as literals: +0 -> +Inf, -0 -> -Inf, +Inf -> +0, negative (including -Inf) -> quiet NaN 0x7E00, NaN -> the same NaN with the quiet bit set (sign and payload kept).

Parameters

Parameters of arm_rsqrt_f16

Name	Type	Direction	Description
input	const float16_t *	in	Pointer to the input tensor.
output	float16_t *	out	Pointer to the output tensor; may alias `input`.
block_size	int32_t	in	Number of tensor elements.

Returns

Returns of arm_rsqrt_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.