Convolution Functions

Collection of convolution, depthwise convolution functions and their variants.

The convolution is implemented in 2 steps: im2col and General Matrix Multiplication(GEMM)

im2col is a process of converting each patch of image data into a column. After im2col, the convolution is computed as matrix-matrix multiplication.

To reduce the memory footprint, the im2col is performed partially. Each iteration, only a few column (i.e., patches) are generated followed by GEMM.

Machine-readable model

• arm_depthwise_nhwc_conv_f32functionDepthwise convolution, NHWC layout.
• arm_depthwise_conv_f32functionDepthwise convolution, dispatch by layout.
• arm_depthwise_conv_wrapper_f32functionDepthwise convolution wrapper using the CMSIS-NN baseline path.
• arm_depthwise_conv_f32_get_buffer_sizefunctionGet the temporary buffer size required by depthwise convolution.
• arm_depthwise_conv_wrapper_f32_get_buffer_sizefunctionGet the buffer size required by the depthwise convolution wrapper.
• arm_convolve_nhwc_f32functionConvolution, NHWC layout.
• arm_convolve_f32functionConvolution, dispatch by layout.
• arm_convolve_wrapper_f32functionConvolution wrapper using the CMSIS-NN baseline path.
• arm_convolve_1x1_nhwc_f32function1x1 convolution, NHWC layout.
• arm_convolve_1x1_nhwc_ohwi_f32function1x1 convolution, NHWC layout.
• arm_convolve_1x1_nhwc_packed_f32function1x1 convolution, NHWC layout.
• arm_convolve_1x1_f32function1x1 convolution, dispatch by layout.
• arm_convolve_1_x_n_nhwc_f32function1xN convolution, NHWC layout.
• arm_convolve_1_x_n_nhwc_ohwi_f32function1xN convolution, NHWC layout.
• arm_convolve_1_x_n_nhwc_packed_f32function1xN convolution, NHWC layout.
• arm_convolve_1_x_n_f32function1xN convolution, dispatch by layout.
• arm_convolve_f32_get_buffer_sizefunctionGet the temporary buffer size required by convolution.
• arm_convolve_wrapper_f32_get_buffer_sizefunctionGet the buffer size required by the convolution wrapper.
• arm_convolve_1x1_f32_get_buffer_sizefunctionGet the buffer size required by 1x1 convolution.
• arm_convolve_1_x_n_f32_get_buffer_sizefunctionGet the buffer size required by 1xN convolution.
• arm_convolve_1d_k5_nhwc_ohwi_f32functionBasic float32 conv1d with a 1x5 filter.
• arm_convolve_1d_k5_nhwc_packed_f32functionBasic float32 conv1d with a 1x5 filter.
• arm_convolve_1d_k3_nhwc_ohwi_f32functionBasic float32 conv1d with a 1x3 filter.
• arm_convolve_1d_k3_nhwc_packed_f32functionBasic float32 conv1d with a 1x3 filter.
• arm_convolve_small_c_nhwc_f32functionBasic float32 direct convolution for small input-channel counts.
• arm_convolve_patch_gemm_nhwc_ohwi_f32functionBasic float32 packed-patch GEMM convolution.
• arm_convolve_patch_gemm_nhwc_packed_f32functionBasic float32 packed-patch GEMM convolution.
• arm_convolve_direct_nhwc_ohwi_f32functionBasic float32 direct convolution.
• arm_convolve_direct_nhwc_packed_f32functionBasic float32 direct convolution.
• arm_convolve_patch_gemm_f32_get_buffer_sizefunctionScratch size in bytes for armconvolvepatchgemmnhwcohwif32() and packedf32(): ARMNNCONVNHWCPATCHGEMMF32MAXTILEROWS patch rows of HK x WK x CIN elements.
• arm_transpose_conv_wrapper_f32functionTranspose convolution wrapper using the CMSIS-NN baseline path.
• arm_transpose_conv_nhwc_f32functionTranspose convolution, NHWC layout.
• arm_transpose_conv_f32functionTranspose convolution, dispatch by layout.
• arm_transpose_conv_f32_get_buffer_sizefunctionGet the temporary buffer size required by transpose convolution.
• arm_transpose_conv_f32_get_reverse_conv_buffer_sizefunctionGet the reverse-convolution workspace size used by transpose convolution helpers.
• arm_depthwise_nhwc_conv_f16functionDepthwise convolution, NHWC layout.
• arm_depthwise_nhwc_conv_f16_acc16functionDepthwise convolution, NHWC layout.
• arm_depthwise_conv_generic_nhwc_f16functionBasic float16 depthwise convolution, NHWC, on the generic route of armdepthwiseconvf16(), as a direct entry: any layer, no scratch.
• arm_depthwise_conv_generic_nhwc_f16_acc16functionBasic float16 depthwise convolution, NHWC, on the generic route of armdepthwiseconvf16(), as a direct entry: any layer, no scratch.
• arm_depthwise_conv_1d_k3_nhwc_f16functionBasic float16 depthwise convolution, NHWC, on the generic route of armdepthwiseconvf16(), as a direct entry: any layer, no scratch.
• arm_depthwise_conv_1d_k3_nhwc_f16_acc16functionBasic float16 depthwise convolution, NHWC, on the generic route of armdepthwiseconvf16(), as a direct entry: any layer, no scratch.
• arm_depthwise_conv_2x5_nhwc_f16functionBasic float16 depthwise convolution, NHWC, on the generic route of armdepthwiseconvf16(), as a direct entry: any layer, no scratch.
• arm_depthwise_conv_2x5_nhwc_f16_acc16functionBasic float16 depthwise convolution, NHWC, on the generic route of armdepthwiseconvf16(), as a direct entry: any layer, no scratch.
• arm_depthwise_conv_direct_nhwc_f16functionBasic float16 depthwise convolution, NHWC, on the generic route of armdepthwiseconvf16(), as a direct entry: any layer, no scratch.
• arm_depthwise_conv_direct_nhwc_f16_acc16functionBasic float16 depthwise convolution, NHWC, on the generic route of armdepthwiseconvf16(), as a direct entry: any layer, no scratch.
• arm_depthwise_conv_cin1_nhwc_f16functionBasic float16 depthwise convolution, NHWC, on the generic route of armdepthwiseconvf16(), as a direct entry: any layer, no scratch.
• arm_depthwise_conv_cin1_nhwc_f16_acc16functionBasic float16 depthwise convolution, NHWC, on the generic route of armdepthwiseconvf16(), as a direct entry: any layer, no scratch.
• arm_depthwise_conv_f16functionDepthwise convolution, dispatch by layout.
• arm_depthwise_conv_f16_acc16functionDepthwise convolution, dispatch by layout.
• arm_depthwise_conv_wrapper_f16functionDepthwise convolution wrapper using the CMSIS-NN baseline path.
• arm_depthwise_conv_wrapper_f16_acc16functionDepthwise convolution wrapper using the CMSIS-NN baseline path.
• arm_depthwise_conv_f16_get_buffer_sizefunctionGet the temporary buffer size required by depthwise convolution.
• arm_depthwise_conv_wrapper_f16_get_buffer_sizefunctionGet the buffer size required by the depthwise convolution wrapper.
• arm_convolve_nhwc_f16functionConvolution, NHWC layout.
• arm_convolve_nhwc_f16_acc16functionConvolution, NHWC layout.
• arm_convolve_f16functionConvolution, dispatch by layout.
• arm_convolve_f16_acc16functionConvolution, dispatch by layout.
• arm_convolve_wrapper_f16functionConvolution wrapper using the CMSIS-NN baseline path.
• arm_convolve_wrapper_f16_acc16functionConvolution wrapper using the CMSIS-NN baseline path.
• arm_convolve_1x1_nhwc_f16function1x1 convolution, NHWC layout.
• arm_convolve_1x1_nhwc_ohwi_f16function1x1 convolution, NHWC layout.
• arm_convolve_1x1_nhwc_packed_f16function1x1 convolution, NHWC layout.
• arm_convolve_1x1_nhwc_f16_acc16function1x1 convolution, NHWC layout.
• arm_convolve_1x1_nhwc_ohwi_f16_acc16function1x1 convolution, NHWC layout.
• arm_convolve_1x1_nhwc_packed_f16_acc16function1x1 convolution, NHWC layout.
• arm_convolve_1x1_f16function1x1 convolution, dispatch by layout.
• arm_convolve_1x1_f16_acc16function1x1 convolution, dispatch by layout.
• arm_convolve_1_x_n_nhwc_f16function1xN convolution, NHWC layout.
• arm_convolve_1_x_n_nhwc_ohwi_f16function1xN convolution, NHWC layout.
• arm_convolve_1_x_n_nhwc_packed_f16function1xN convolution, NHWC layout.
• arm_convolve_1_x_n_nhwc_f16_acc16function1xN convolution, NHWC layout.
• arm_convolve_1_x_n_nhwc_ohwi_f16_acc16function1xN convolution, NHWC layout.
• arm_convolve_1_x_n_nhwc_packed_f16_acc16function1xN convolution, NHWC layout.
• arm_convolve_1_x_n_f16function1xN convolution, dispatch by layout.
• arm_convolve_1_x_n_f16_acc16function1xN convolution, dispatch by layout.
• arm_convolve_f16_get_buffer_sizefunctionGet the temporary buffer size required by convolution.
• arm_convolve_wrapper_f16_get_buffer_sizefunctionGet the buffer size required by the convolution wrapper.
• arm_convolve_1x1_f16_get_buffer_sizefunctionGet the buffer size required by 1x1 convolution.
• arm_convolve_1_x_n_f16_get_buffer_sizefunctionGet the buffer size required by 1xN convolution.
• arm_convolve_1d_k5_nhwc_ohwi_f16functionBasic float32 conv1d with a 1x5 filter.
• arm_convolve_1d_k5_nhwc_ohwi_f16_acc16functionBasic float32 conv1d with a 1x5 filter.
• arm_convolve_1d_k5_nhwc_packed_f16functionBasic float32 conv1d with a 1x5 filter.
• arm_convolve_1d_k5_nhwc_packed_f16_acc16functionBasic float32 conv1d with a 1x5 filter.
• arm_convolve_1d_k3_nhwc_ohwi_f16functionBasic float32 conv1d with a 1x3 filter.
• arm_convolve_1d_k3_nhwc_ohwi_f16_acc16functionBasic float32 conv1d with a 1x3 filter.
• arm_convolve_1d_k3_nhwc_packed_f16functionBasic float32 conv1d with a 1x3 filter.
• arm_convolve_1d_k3_nhwc_packed_f16_acc16functionBasic float32 conv1d with a 1x3 filter.
• arm_convolve_small_c_nhwc_f16functionBasic float32 direct convolution for small input-channel counts.
• arm_convolve_patch_gemm_nhwc_ohwi_f16functionBasic float32 packed-patch GEMM convolution.
• arm_convolve_patch_gemm_nhwc_ohwi_f16_acc16functionBasic float32 packed-patch GEMM convolution.
• arm_convolve_patch_gemm_nhwc_packed_f16functionBasic float32 packed-patch GEMM convolution.
• arm_convolve_patch_gemm_nhwc_packed_f16_acc16functionBasic float32 packed-patch GEMM convolution.
• arm_convolve_direct_nhwc_ohwi_f16functionBasic float32 direct convolution.
• arm_convolve_direct_nhwc_ohwi_f16_acc16functionBasic float32 direct convolution.
• arm_convolve_direct_nhwc_packed_f16functionBasic float32 direct convolution.
• arm_convolve_direct_nhwc_packed_f16_acc16functionBasic float32 direct convolution.
• arm_convolve_patch_gemm_f16_get_buffer_sizefunctionScratch size in bytes for armconvolvepatchgemmnhwcohwif32() and packedf32(): ARMNNCONVNHWCPATCHGEMMF32MAXTILEROWS patch rows of HK x WK x CIN elements.
• arm_transpose_conv_wrapper_f16functionTranspose convolution wrapper using the CMSIS-NN baseline path.
• arm_transpose_conv_nhwc_f16functionTranspose convolution, NHWC layout.
• arm_transpose_conv_f16functionTranspose convolution, dispatch by layout.
• arm_transpose_conv_f16_get_buffer_sizefunctionGet the temporary buffer size required by transpose convolution.
• arm_transpose_conv_f16_get_reverse_conv_buffer_sizefunctionGet the reverse-convolution workspace size used by transpose convolution helpers.

function

arm_depthwise_nhwc_conv_f32

C

Depthwise convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:79

arm_cmsis_nn_status arm_depthwise_nhwc_conv_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_dw_conv_params_f32 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input,
    const cmsis_nn_dims *filter_dims,
    const float32_t *kernel,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias,
    const cmsis_nn_dims *output_dims,
    float32_t *output
)

Depthwise convolution, NHWC layout.

Note

When ctx->buf is used for internal kernel repacking, it must be aligned to the element type stored in scratch: at least 4-byte aligned for float32_t and at least 2-byte aligned for float16_t.

Note

Accumulation and NaN, per leg (AmbiqAI/ns-cmsis-nn#448). Every route accumulates the bias and every tap in float32 on every leg. A NaN input tap or weight does not propagate: the ch_mult == 1 direct kernel’s MVE leg clamps it to the activation minimum (vmaxnm / vminnm); the MVE to-convolution route (input channels 1, output channels 8 or more, ctx supplied) clamps it to the activation minimum (arm_nn_clamp_mve_f32); its scalar leg and the ch_mult > 1 generic kernel clamp it to the activation maximum (ARM_NN_CLAMP). That is the pre-#448 behavior of these routes; unifying it with the float16 scalar leg under the #334 promise is a separate issue.

Parameters

Parameters of arm_depthwise_nhwc_conv_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
dw_conv_params	const cmsis_nn_dw_conv_params_f32 *	in	Depthwise convolution parameters (stride, padding, dilation, channel multiplier and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions in NHWC format.
input	const float32_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions in NHWC-compatible depthwise format.
kernel	const float32_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias	const float32_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions in NHWC format.
output	float32_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_depthwise_nhwc_conv_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_depthwise_conv_f32

C

Depthwise convolution, dispatch by layout.

Include/arm_nnfunctions_flt.h:119

arm_cmsis_nn_status arm_depthwise_conv_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_dw_conv_params_f32 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input,
    const cmsis_nn_dims *filter_dims,
    const float32_t *kernel,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias,
    const cmsis_nn_dims *output_dims,
    float32_t *output,
    arm_nn_tensor_layout layout
)

Depthwise convolution, dispatch by layout.

Note

When ctx->buf is used for internal kernel repacking, it must be aligned to the element type stored in scratch: at least 4-byte aligned for float32_t and at least 2-byte aligned for float16_t.

Note

Accumulation and NaN, per leg (AmbiqAI/ns-cmsis-nn#448). Every route accumulates the bias and every tap in float32 on every leg. A NaN input tap or weight does not propagate: the ch_mult == 1 direct kernel’s MVE leg clamps it to the activation minimum (vmaxnm / vminnm); the MVE to-convolution route (input channels 1, output channels 8 or more, ctx supplied) clamps it to the activation minimum (arm_nn_clamp_mve_f32); its scalar leg and the ch_mult > 1 generic kernel clamp it to the activation maximum (ARM_NN_CLAMP). That is the pre-#448 behavior of these routes; unifying it with the float16 scalar leg under the #334 promise is a separate issue.

Parameters

Parameters of arm_depthwise_conv_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
dw_conv_params	const cmsis_nn_dw_conv_params_f32 *	in	Depthwise convolution parameters (stride, padding, dilation, channel multiplier and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format depends on `layout`.
input	const float32_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format depends on `layout`.
kernel	const float32_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias	const float32_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format depends on `layout`.
output	float32_t *	out	Pointer to the output tensor data.
layout	arm_nn_tensor_layout	in	Tensor layout selector. Current float APIs require `ARM_NN_LAYOUT_NHWC`.

Returns

Returns of arm_depthwise_conv_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_depthwise_conv_wrapper_f32

C

Depthwise convolution wrapper using the CMSIS-NN baseline path.

Include/arm_nnfunctions_flt.h:158

arm_cmsis_nn_status arm_depthwise_conv_wrapper_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_dw_conv_params_f32 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input,
    const cmsis_nn_dims *filter_dims,
    const float32_t *kernel,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias,
    const cmsis_nn_dims *output_dims,
    float32_t *output
)

Depthwise convolution wrapper using the CMSIS-NN baseline path.

Note

When ctx->buf is used for internal kernel repacking, it must be aligned to the element type stored in scratch: at least 4-byte aligned for float32_t and at least 2-byte aligned for float16_t.

Note

Accumulation and NaN, per leg (AmbiqAI/ns-cmsis-nn#448). Every route accumulates the bias and every tap in float32 on every leg. A NaN input tap or weight does not propagate: the ch_mult == 1 direct kernel’s MVE leg clamps it to the activation minimum (vmaxnm / vminnm); the MVE to-convolution route (input channels 1, output channels 8 or more, ctx supplied) clamps it to the activation minimum (arm_nn_clamp_mve_f32); its scalar leg and the ch_mult > 1 generic kernel clamp it to the activation maximum (ARM_NN_CLAMP). That is the pre-#448 behavior of these routes; unifying it with the float16 scalar leg under the #334 promise is a separate issue.

Parameters

Parameters of arm_depthwise_conv_wrapper_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
dw_conv_params	const cmsis_nn_dw_conv_params_f32 *	in	Depthwise convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
input	const float32_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
kernel	const float32_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias	const float32_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions.
output	float32_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_depthwise_conv_wrapper_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_depthwise_conv_f32_get_buffer_size

C

Get the temporary buffer size required by depthwise convolution.

Include/arm_nnfunctions_flt.h:193

int32_t arm_depthwise_conv_f32_get_buffer_size(
    const cmsis_nn_dw_conv_params_f32 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const cmsis_nn_dims *filter_dims,
    const cmsis_nn_dims *output_dims,
    arm_nn_tensor_layout layout
)

Get the temporary buffer size required by depthwise convolution.

Note

Only one route reads scratch: on MVE builds, an NHWC depthwise with ch_mult != 1, a single input channel and at least CONVERT_DW_CONV_WITH_ONE_INPUT_CH_AND_OUTPUT_CH_ABOVE_THRESHOLD output channels can run as a regular convolution, which needs the repacked filter, ROUND_UP(output_dims->c, 4) * filter_dims->h * filter_dims->w * sizeof(float32_t) bytes (ROUND_UP(output_dims->c, 8) and sizeof(float16_t) for _f16), plus arm_convolve_wrapper_f32_get_buffer_size for that convolution. For _f16, the added workspace is the larger of arm_convolve_wrapper_f16_get_buffer_size and one patch row of filter_dims->h * filter_dims->w * sizeof(float16_t) bytes. The query reserves that for every such layer; one an exact-shape specialization takes first runs without it, so the size is an upper bound there. Every other layer the ch_mult == 1 direct kernel and the generic kernel runs without scratch and the query returns 0 (AmbiqAI/ns-cmsis-nn#448, #625). For _f16 the convolution route serves the _acc16 entries; the default entries’ one-input-channel kernel reads none of this ctx but takes the route only when ctx holds it, and otherwise runs the generic kernel (#830).

Parameters

Parameters of arm_depthwise_conv_f32_get_buffer_size

Name	Type	Direction	Description
dw_conv_params	const cmsis_nn_dw_conv_params_f32 *	in	Depthwise convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions.
layout	arm_nn_tensor_layout	in	Tensor layout selector.

Returns

Returns of arm_depthwise_conv_f32_get_buffer_size

Description
Required buffer size in bytes, or 0 when no scratch buffer is needed.

function

arm_depthwise_conv_wrapper_f32_get_buffer_size

C

Get the buffer size required by the depthwise convolution wrapper.

Include/arm_nnfunctions_flt.h:209

int32_t arm_depthwise_conv_wrapper_f32_get_buffer_size(
    const cmsis_nn_dw_conv_params_f32 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const cmsis_nn_dims *filter_dims,
    const cmsis_nn_dims *output_dims
)

Get the buffer size required by the depthwise convolution wrapper.

Parameters

Parameters of arm_depthwise_conv_wrapper_f32_get_buffer_size

Name	Type	Direction	Description
dw_conv_params	const cmsis_nn_dw_conv_params_f32 *	in	Depthwise convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions.

Returns

Returns of arm_depthwise_conv_wrapper_f32_get_buffer_size

Description
Required buffer size in bytes, or 0 when no scratch buffer is needed.

function

arm_convolve_nhwc_f32

C

Convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:244

arm_cmsis_nn_status arm_convolve_nhwc_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data
)

Convolution, NHWC layout.

Note

Dimensions must be nonnegative and batch/channel/filter metadata must agree. Stride and dilation are positive; padding is nonnegative. Nonempty work requires positive input spatial/filter/channel extents and representable accessed products and coordinates. Invalid arguments return ARG_ERROR without output writes. Valid zero batch or output spatial extent returns SUCCESS without tensor access. Generic output windows are explicit and out-of-input taps are clipped; an unsafe specialization is declined rather than imposing a derived output shape. Pointer validity, aliasing and allocation lengths remain the caller’s responsibility. Bias may be NULL.

Note

When conv_params->weight_format is set to ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, every convolution path, including the 1xN kernels and the generic fallback that runs without scratch, interprets filter_data as an already prepacked NTxN RHS buffer instead of the standard public filter layout.

Parameters

Parameters of arm_convolve_nhwc_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float32_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float32_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float32_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float32_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_nhwc_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_f32

C

Convolution, dispatch by layout.

Include/arm_nnfunctions_flt.h:278

arm_cmsis_nn_status arm_convolve_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data,
    arm_nn_tensor_layout layout
)

Convolution, dispatch by layout.

Note

When conv_params->weight_format is set to ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, every convolution path, including the 1xN kernels and the generic fallback that runs without scratch, interprets filter_data as an already prepacked NTxN RHS buffer instead of the standard public filter layout.

Parameters

Parameters of arm_convolve_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format depends on `layout`.
input_data	const float32_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format depends on `layout`.
filter_data	const float32_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float32_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format depends on `layout`.
output_data	float32_t *	out	Pointer to the output tensor data.
layout	arm_nn_tensor_layout	in	Tensor layout selector. Current float APIs require `ARM_NN_LAYOUT_NHWC`.

Returns

Returns of arm_convolve_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_wrapper_f32

C

Convolution wrapper using the CMSIS-NN baseline path.

Include/arm_nnfunctions_flt.h:306

arm_cmsis_nn_status arm_convolve_wrapper_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data
)

Convolution wrapper using the CMSIS-NN baseline path.

Parameters

Parameters of arm_convolve_wrapper_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float32_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float32_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float32_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float32_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_wrapper_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1x1_nhwc_f32

C

1x1 convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:333

arm_cmsis_nn_status arm_convolve_1x1_nhwc_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data
)

1x1 convolution, NHWC layout.

Parameters

Parameters of arm_convolve_1x1_nhwc_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float32_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float32_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float32_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float32_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_1x1_nhwc_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1x1_nhwc_ohwi_f32

C

1x1 convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:352

arm_cmsis_nn_status arm_convolve_1x1_nhwc_ohwi_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data
)

1x1 convolution, NHWC layout.

Note

For ARM_NN_WEIGHT_FORMAT_STANDARD filters only, so that an image links only that format’s kernels; returns ARM_CMSIS_NN_NO_IMPL_ERROR and writes nothing for ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters. A filter other than 1x1, or any padding, returns ARM_CMSIS_NN_ARG_ERROR, as the format-agnostic function does; the filter format is checked first.

Parameters

Parameters of arm_convolve_1x1_nhwc_ohwi_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float32_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float32_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float32_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float32_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_1x1_nhwc_ohwi_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1x1_nhwc_packed_f32

C

1x1 convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:371

arm_cmsis_nn_status arm_convolve_1x1_nhwc_packed_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data
)

1x1 convolution, NHWC layout.

Note

For ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters only, so that an image links only that format’s kernels; returns ARM_CMSIS_NN_NO_IMPL_ERROR and writes nothing for ARM_NN_WEIGHT_FORMAT_STANDARD filters. A filter other than 1x1, or any padding, returns ARM_CMSIS_NN_ARG_ERROR, as the format-agnostic function does; the filter format is checked first.

Parameters

Parameters of arm_convolve_1x1_nhwc_packed_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float32_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float32_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float32_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float32_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_1x1_nhwc_packed_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1x1_f32

C

1x1 convolution, dispatch by layout.

Include/arm_nnfunctions_flt.h:404

arm_cmsis_nn_status arm_convolve_1x1_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data,
    arm_nn_tensor_layout layout
)

1x1 convolution, dispatch by layout.

Note

When conv_params->weight_format is set to ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, the matmul-backed 1x1 convolution paths interpret filter_data as an already prepacked NTxN RHS buffer instead of the standard public filter layout.

Parameters

Parameters of arm_convolve_1x1_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format depends on `layout`.
input_data	const float32_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format depends on `layout`.
filter_data	const float32_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float32_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format depends on `layout`.
output_data	float32_t *	out	Pointer to the output tensor data.
layout	arm_nn_tensor_layout	in	Tensor layout selector. Current float APIs require `ARM_NN_LAYOUT_NHWC`.

Returns

Returns of arm_convolve_1x1_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1_x_n_nhwc_f32

C

1xN convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:448

arm_cmsis_nn_status arm_convolve_1_x_n_nhwc_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data
)

1xN convolution, NHWC layout.

Note

When conv_params->weight_format is set to ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, filter_data is interpreted as an already prepacked NTxN RHS buffer instead of the standard public filter layout. Every output position, including the no-pad middle region that OHWI filters take straight from the input, is then packed into scratch and multiplied by the format-aware matmul, so a packed 1xN layer with little or no padding runs slower than its OHWI equivalent.

Note

On MVE builds, with OHWI filters, the no-padding positions run row by row, read in place, through the contiguous-K matmul when the layer has at least 4 output channels and 224 taps (filter width times input channels), and through a strided kernel otherwise. The float16 entries also do so from 80 taps when 4 to 7 output channels remain in the last 8-channel block.

Parameters

Parameters of arm_convolve_1_x_n_nhwc_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float32_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float32_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float32_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float32_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_1_x_n_nhwc_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1_x_n_nhwc_ohwi_f32

C

1xN convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:468

arm_cmsis_nn_status arm_convolve_1_x_n_nhwc_ohwi_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data
)

1xN convolution, NHWC layout.

Note

When conv_params->weight_format is set to ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, filter_data is interpreted as an already prepacked NTxN RHS buffer instead of the standard public filter layout. Every output position, including the no-pad middle region that OHWI filters take straight from the input, is then packed into scratch and multiplied by the format-aware matmul, so a packed 1xN layer with little or no padding runs slower than its OHWI equivalent.

Note

On MVE builds, with OHWI filters, the no-padding positions run row by row, read in place, through the contiguous-K matmul when the layer has at least 4 output channels and 224 taps (filter width times input channels), and through a strided kernel otherwise. The float16 entries also do so from 80 taps when 4 to 7 output channels remain in the last 8-channel block.

Note

For ARM_NN_WEIGHT_FORMAT_STANDARD filters only, so that an image links only that format’s kernels; returns ARM_CMSIS_NN_NO_IMPL_ERROR and writes nothing for ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters. A missing ctx, a layer that is not 1xN or an input depth that differs from the filter’s returns ARM_CMSIS_NN_ARG_ERROR before the filter format is checked, and a ctx smaller than the size query returns it after; as the format-agnostic function does.

Parameters

Parameters of arm_convolve_1_x_n_nhwc_ohwi_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float32_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float32_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float32_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float32_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_1_x_n_nhwc_ohwi_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1_x_n_nhwc_packed_f32

C

1xN convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:488

arm_cmsis_nn_status arm_convolve_1_x_n_nhwc_packed_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data
)

1xN convolution, NHWC layout.

Note

When conv_params->weight_format is set to ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, filter_data is interpreted as an already prepacked NTxN RHS buffer instead of the standard public filter layout. Every output position, including the no-pad middle region that OHWI filters take straight from the input, is then packed into scratch and multiplied by the format-aware matmul, so a packed 1xN layer with little or no padding runs slower than its OHWI equivalent.

Note

On MVE builds, with OHWI filters, the no-padding positions run row by row, read in place, through the contiguous-K matmul when the layer has at least 4 output channels and 224 taps (filter width times input channels), and through a strided kernel otherwise. The float16 entries also do so from 80 taps when 4 to 7 output channels remain in the last 8-channel block.

Note

For ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters only, so that an image links only that format’s kernels; returns ARM_CMSIS_NN_NO_IMPL_ERROR and writes nothing for ARM_NN_WEIGHT_FORMAT_STANDARD filters. A missing ctx, a layer that is not 1xN or an input depth that differs from the filter’s returns ARM_CMSIS_NN_ARG_ERROR before the filter format is checked, and a ctx smaller than the size query returns it after; as the format-agnostic function does.

Parameters

Parameters of arm_convolve_1_x_n_nhwc_packed_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float32_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float32_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float32_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float32_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_1_x_n_nhwc_packed_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1_x_n_f32

C

1xN convolution, dispatch by layout.

Include/arm_nnfunctions_flt.h:532

arm_cmsis_nn_status arm_convolve_1_x_n_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data,
    arm_nn_tensor_layout layout
)

1xN convolution, dispatch by layout.

Note

When conv_params->weight_format is set to ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, filter_data is interpreted as an already prepacked NTxN RHS buffer instead of the standard public filter layout. Every output position, including the no-pad middle region that OHWI filters take straight from the input, is then packed into scratch and multiplied by the format-aware matmul, so a packed 1xN layer with little or no padding runs slower than its OHWI equivalent.

Note

On MVE builds, with OHWI filters, the no-padding positions run row by row, read in place, through the contiguous-K matmul when the layer has at least 4 output channels and 224 taps (filter width times input channels), and through a strided kernel otherwise. The float16 entries also do so from 80 taps when 4 to 7 output channels remain in the last 8-channel block.

Parameters

Parameters of arm_convolve_1_x_n_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format depends on `layout`.
input_data	const float32_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format depends on `layout`.
filter_data	const float32_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float32_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format depends on `layout`.
output_data	float32_t *	out	Pointer to the output tensor data.
layout	arm_nn_tensor_layout	in	Tensor layout selector. Current float APIs require `ARM_NN_LAYOUT_NHWC`.

Returns

Returns of arm_convolve_1_x_n_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_f32_get_buffer_size

C

Get the temporary buffer size required by convolution.

Include/arm_nnfunctions_flt.h:560

int32_t arm_convolve_f32_get_buffer_size(
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const cmsis_nn_dims *filter_dims,
    const cmsis_nn_dims *output_dims,
    arm_nn_tensor_layout layout
)

Get the temporary buffer size required by convolution.

Note

When conv_params->weight_format is ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, this still reports only the temporary input/im2col scratch requirement. Any offline-packed filter storage is expected to be provided by the caller.

Parameters

Parameters of arm_convolve_f32_get_buffer_size

Name	Type	Direction	Description
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions.
layout	arm_nn_tensor_layout	in	Tensor layout selector.

Returns

Returns of arm_convolve_f32_get_buffer_size

Description
Required buffer size in bytes, or 0 when no scratch buffer is needed.

function

arm_convolve_wrapper_f32_get_buffer_size

C

Get the buffer size required by the convolution wrapper.

Include/arm_nnfunctions_flt.h:576

int32_t arm_convolve_wrapper_f32_get_buffer_size(
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const cmsis_nn_dims *filter_dims,
    const cmsis_nn_dims *output_dims
)

Get the buffer size required by the convolution wrapper.

Parameters

Parameters of arm_convolve_wrapper_f32_get_buffer_size

Name	Type	Direction	Description
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions.

Returns

Returns of arm_convolve_wrapper_f32_get_buffer_size

Description
Required buffer size in bytes, or 0 when no scratch buffer is needed.

function

arm_convolve_1x1_f32_get_buffer_size

C

Get the buffer size required by 1x1 convolution.

Include/arm_nnfunctions_flt.h:597

int32_t arm_convolve_1x1_f32_get_buffer_size(
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const cmsis_nn_dims *filter_dims,
    const cmsis_nn_dims *output_dims,
    arm_nn_tensor_layout layout
)

Get the buffer size required by 1x1 convolution.

Note

Returns 0 for the unity-stride no-pack path. For non-unity-stride NHWC 1x1 convolution, the returned scratch size enables the packed-tile + GEMM path. When conv_params->weight_format is ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, this still excludes the offline-packed filter storage itself.

Parameters

Parameters of arm_convolve_1x1_f32_get_buffer_size

Name	Type	Direction	Description
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions.
layout	arm_nn_tensor_layout	in	Tensor layout selector.

Returns

Returns of arm_convolve_1x1_f32_get_buffer_size

Description
Required buffer size in bytes, or 0 when no scratch buffer is needed.

function

arm_convolve_1_x_n_f32_get_buffer_size

C

Get the buffer size required by 1xN convolution.

Include/arm_nnfunctions_flt.h:614

int32_t arm_convolve_1_x_n_f32_get_buffer_size(
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const cmsis_nn_dims *filter_dims,
    const cmsis_nn_dims *output_dims,
    arm_nn_tensor_layout layout
)

Get the buffer size required by 1xN convolution.

Parameters

Parameters of arm_convolve_1_x_n_f32_get_buffer_size

Name	Type	Direction	Description
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions.
layout	arm_nn_tensor_layout	in	Tensor layout selector.

Returns

Returns of arm_convolve_1_x_n_f32_get_buffer_size

Description
Required buffer size in bytes, or 0 when no scratch buffer is needed.

function

arm_convolve_1d_k5_nhwc_ohwi_f32

C

Basic float32 conv1d with a 1x5 filter.

Include/arm_nnfunctions_flt.h:653

arm_cmsis_nn_status arm_convolve_1d_k5_nhwc_ohwi_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data
)

Basic float32 conv1d with a 1x5 filter.

The conv1d k5 route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry.

• Gate: arm_nn_conv_flt_is_1d_k with k = 5: batch 1, input and output height 1, a 1x5 filter, unit stride and dilation, no padding. No scratch.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_1d_k5_nhwc_ohwi_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float32_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float32_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float32_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float32_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_1d_k5_nhwc_ohwi_f32

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL `ARM_CMSIS_NN_NO_IMPL_ERROR` - the layer is not the shape arm_nn_conv_flt_is_1d_k accepts with k = 5, or the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_1d_k5_nhwc_packed_f32

C

Basic float32 conv1d with a 1x5 filter.

Include/arm_nnfunctions_flt.h:667

arm_cmsis_nn_status arm_convolve_1d_k5_nhwc_packed_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data
)

Basic float32 conv1d with a 1x5 filter.

The conv1d k5 route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry.

• Gate: arm_nn_conv_flt_is_1d_k with k = 5: batch 1, input and output height 1, a 1x5 filter, unit stride and dilation, no padding. No scratch.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_1d_k5_nhwc_packed_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float32_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float32_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float32_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float32_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_1d_k5_nhwc_packed_f32

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL `ARM_CMSIS_NN_NO_IMPL_ERROR` - the layer is not the shape arm_nn_conv_flt_is_1d_k accepts with k = 5, or the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_1d_k3_nhwc_ohwi_f32

C

Basic float32 conv1d with a 1x3 filter.

Include/arm_nnfunctions_flt.h:710

arm_cmsis_nn_status arm_convolve_1d_k3_nhwc_ohwi_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data
)

Basic float32 conv1d with a 1x3 filter.

The conv1d k3 route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry.

• Gate: arm_nn_conv_flt_is_1d_k with k = 3. No scratch.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_1d_k3_nhwc_ohwi_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float32_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float32_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float32_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float32_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_1d_k3_nhwc_ohwi_f32

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL `ARM_CMSIS_NN_NO_IMPL_ERROR` - the layer is not the shape arm_nn_conv_flt_is_1d_k accepts with k = 3, or the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_1d_k3_nhwc_packed_f32

C

Basic float32 conv1d with a 1x3 filter.

Include/arm_nnfunctions_flt.h:724

arm_cmsis_nn_status arm_convolve_1d_k3_nhwc_packed_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data
)

Basic float32 conv1d with a 1x3 filter.

The conv1d k3 route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry.

• Gate: arm_nn_conv_flt_is_1d_k with k = 3. No scratch.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_1d_k3_nhwc_packed_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float32_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float32_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float32_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float32_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_1d_k3_nhwc_packed_f32

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL `ARM_CMSIS_NN_NO_IMPL_ERROR` - the layer is not the shape arm_nn_conv_flt_is_1d_k accepts with k = 3, or the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_small_c_nhwc_f32

C

Basic float32 direct convolution for small input-channel counts.

Include/arm_nnfunctions_flt.h:769

arm_cmsis_nn_status arm_convolve_small_c_nhwc_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data
)

Basic float32 direct convolution for small input-channel counts.

The small-C route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry. Lanes are output x positions and weights are scalars.

• Gate: arm_nn_conv_f32_is_small_c or arm_nn_conv_f32_is_small_c_3x3 for float32, subject to arm_nn_conv_f32_small_c_coords_ok; arm_nn_conv_f16_is_small_c for float16. Either filter format; the format changes only the weight stride inside one kernel. No scratch. The additional float32 region uses 3x3 filters, four input channels, at most eight output channels and at least four output columns.
• arm_convolve_small_c_nhwc_f16() takes the same arguments and return codes. It accumulates in float32, the kernel both arm_convolve_f16() and arm_convolve_f16_acc16() run on this route. For 3x3 filters, 2..3 input channels and output height/width >= 32, it caches two channels of weights in a fixed 216-byte stack buffer. Other admitted shapes use the uncached kernel. Neither path needs caller scratch.

Parameters

Parameters of arm_convolve_small_c_nhwc_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float32_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float32_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float32_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float32_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_small_c_nhwc_f32

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL `ARM_CMSIS_NN_NO_IMPL_ERROR` - the layer is outside the gate, or the build lacks MVE float (ARM_MATH_MVEF for float32, ARM_MATH_MVE_FLOAT16 for float16) or defines ARM_MATH_AUTOVECTORIZE; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_patch_gemm_nhwc_ohwi_f32

C

Basic float32 packed-patch GEMM convolution.

Include/arm_nnfunctions_flt.h:816

arm_cmsis_nn_status arm_convolve_patch_gemm_nhwc_ohwi_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data
)

Basic float32 packed-patch GEMM convolution.

The packed-patch GEMM route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry: up to ARM_NN_CONV_NHWC_PATCH_GEMM_F32_MAX_TILE_ROWS output positions at a time are packed into ctx as patch rows and multiplied with the filter.

• Valid for any NHWC layer. The router takes it when arm_nn_conv_flt_is_patch_gemm holds and ctx holds one patch row; unlike the router, the entry does not fall back to the direct route.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_patch_gemm_nhwc_ohwi_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Scratch buffer of at least one patch row (HK x WK x C_IN elements); `arm_convolve_patch_gemm_f32_get_buffer_size()` gives the size for full tiles
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float32_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float32_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float32_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float32_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_patch_gemm_nhwc_ohwi_f32

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL, or ctx, ctx->buf is NULL or ctx->size is below one patch row `ARM_CMSIS_NN_NO_IMPL_ERROR` - the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_patch_gemm_nhwc_packed_f32

C

Basic float32 packed-patch GEMM convolution.

Include/arm_nnfunctions_flt.h:830

arm_cmsis_nn_status arm_convolve_patch_gemm_nhwc_packed_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data
)

Basic float32 packed-patch GEMM convolution.

The packed-patch GEMM route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry: up to ARM_NN_CONV_NHWC_PATCH_GEMM_F32_MAX_TILE_ROWS output positions at a time are packed into ctx as patch rows and multiplied with the filter.

• Valid for any NHWC layer. The router takes it when arm_nn_conv_flt_is_patch_gemm holds and ctx holds one patch row; unlike the router, the entry does not fall back to the direct route.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_patch_gemm_nhwc_packed_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Scratch buffer of at least one patch row (HK x WK x C_IN elements); `arm_convolve_patch_gemm_f32_get_buffer_size()` gives the size for full tiles
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float32_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float32_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float32_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float32_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_patch_gemm_nhwc_packed_f32

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL, or ctx, ctx->buf is NULL or ctx->size is below one patch row `ARM_CMSIS_NN_NO_IMPL_ERROR` - the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_direct_nhwc_ohwi_f32

C

Basic float32 direct convolution.

Include/arm_nnfunctions_flt.h:873

arm_cmsis_nn_status arm_convolve_direct_nhwc_ohwi_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data
)

Basic float32 direct convolution.

The direct route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry: the route the routers take when no other route claims the layer.

• Valid for any NHWC layer. No scratch.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_direct_nhwc_ohwi_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float32_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float32_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float32_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float32_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_direct_nhwc_ohwi_f32

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL `ARM_CMSIS_NN_NO_IMPL_ERROR` - the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_direct_nhwc_packed_f32

C

Basic float32 direct convolution.

Include/arm_nnfunctions_flt.h:887

arm_cmsis_nn_status arm_convolve_direct_nhwc_packed_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data
)

Basic float32 direct convolution.

The direct route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry: the route the routers take when no other route claims the layer.

• Valid for any NHWC layer. No scratch.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_direct_nhwc_packed_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float32_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float32_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float32_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float32_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_direct_nhwc_packed_f32

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL `ARM_CMSIS_NN_NO_IMPL_ERROR` - the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_patch_gemm_f32_get_buffer_size

C

Scratch size in bytes for armconvolvepatchgemmnhwcohwif32() and packedf32(): ARMNNCONVNHWCPATCHGEMMF32MAXTILEROWS patch rows of HK x WK x CIN elements.

Include/arm_nnfunctions_flt.h:910

int32_t arm_convolve_patch_gemm_f32_get_buffer_size(
    const cmsis_nn_conv_params_f32 *conv_params,
    const cmsis_nn_dims *input_dims,
    const cmsis_nn_dims *filter_dims,
    const cmsis_nn_dims *output_dims
)

Scratch size in bytes for arm_convolve_patch_gemm_nhwc_ohwi_f32() and _packed_f32(): ARM_NN_CONV_NHWC_PATCH_GEMM_F32_MAX_TILE_ROWS patch rows of HK x WK x C_IN elements.

Parameters

Parameters of arm_convolve_patch_gemm_f32_get_buffer_size

Name	Type	Direction	Description
conv_params	const cmsis_nn_conv_params_f32 *	in	Convolution parameters
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]

Returns

Returns of arm_convolve_patch_gemm_f32_get_buffer_size

Description
The size in bytes, or 0 for a NULL argument, a non-positive C_IN, HK, WK or C_OUT, or a size above INT32_MAX

function

arm_transpose_conv_wrapper_f32

C

Transpose convolution wrapper using the CMSIS-NN baseline path.

Include/arm_nnfunctions_flt.h:2090

arm_cmsis_nn_status arm_transpose_conv_wrapper_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_context *output_ctx,
    const cmsis_nn_transpose_conv_params_f32 *transpose_conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data,
    arm_nn_tensor_layout layout
)

Transpose convolution wrapper using the CMSIS-NN baseline path.

Parameters

Parameters of arm_transpose_conv_wrapper_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Function context. Unused; may be NULL.
output_ctx	const cmsis_nn_context *	in	Output context. Unused; may be NULL.
transpose_conv_params	const cmsis_nn_transpose_conv_params_f32 *	in	Transpose convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
input_data	const float32_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
filter_data	const float32_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions.
bias_data	const float32_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions.
output_data	float32_t *	out	Pointer to the output tensor data.
layout	arm_nn_tensor_layout	in	Tensor layout selector. Current float APIs require `ARM_NN_LAYOUT_NHWC`.

Returns

Returns of arm_transpose_conv_wrapper_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_transpose_conv_nhwc_f32

C

Transpose convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:2120

arm_cmsis_nn_status arm_transpose_conv_nhwc_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_context *output_ctx,
    const cmsis_nn_transpose_conv_params_f32 *transpose_conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data
)

Transpose convolution, NHWC layout.

Parameters

Parameters of arm_transpose_conv_nhwc_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Function context. Unused; may be NULL.
output_ctx	const cmsis_nn_context *	in	Output context. Unused; may be NULL.
transpose_conv_params	const cmsis_nn_transpose_conv_params_f32 *	in	Transpose convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
input_data	const float32_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
filter_data	const float32_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions.
bias_data	const float32_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions.
output_data	float32_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_transpose_conv_nhwc_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_transpose_conv_f32

C

Transpose convolution, dispatch by layout.

Include/arm_nnfunctions_flt.h:2150

arm_cmsis_nn_status arm_transpose_conv_f32(
    const cmsis_nn_context *ctx,
    const cmsis_nn_context *output_ctx,
    const cmsis_nn_transpose_conv_params_f32 *transpose_conv_params,
    const cmsis_nn_dims *input_dims,
    const float32_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float32_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float32_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float32_t *output_data,
    arm_nn_tensor_layout layout
)

Transpose convolution, dispatch by layout.

Parameters

Parameters of arm_transpose_conv_f32

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Function context. Unused; may be NULL.
output_ctx	const cmsis_nn_context *	in	Output context. Unused; may be NULL.
transpose_conv_params	const cmsis_nn_transpose_conv_params_f32 *	in	Transpose convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
input_data	const float32_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
filter_data	const float32_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions.
bias_data	const float32_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions.
output_data	float32_t *	out	Pointer to the output tensor data.
layout	arm_nn_tensor_layout	in	Tensor layout selector. Current float APIs require `ARM_NN_LAYOUT_NHWC`.

Returns

Returns of arm_transpose_conv_f32

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_transpose_conv_f32_get_buffer_size

C

Get the temporary buffer size required by transpose convolution.

Include/arm_nnfunctions_flt.h:2173

int32_t arm_transpose_conv_f32_get_buffer_size(
    const cmsis_nn_transpose_conv_params_f32 *transpose_conv_params,
    const cmsis_nn_dims *input_dims,
    const cmsis_nn_dims *filter_dims,
    const cmsis_nn_dims *out_dims
)

Get the temporary buffer size required by transpose convolution.

Parameters

Parameters of arm_transpose_conv_f32_get_buffer_size

Name	Type	Direction	Description
transpose_conv_params	const cmsis_nn_transpose_conv_params_f32 *	in	Transpose convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
out_dims	const cmsis_nn_dims *	in	Output tensor dimensions.

Returns

Returns of arm_transpose_conv_f32_get_buffer_size

Description
Required buffer size in bytes, or 0 when no scratch buffer is needed.

function

arm_transpose_conv_f32_get_reverse_conv_buffer_size

C

Get the reverse-convolution workspace size used by transpose convolution helpers.

Include/arm_nnfunctions_flt.h:2188

int32_t arm_transpose_conv_f32_get_reverse_conv_buffer_size(
    const cmsis_nn_transpose_conv_params_f32 *transpose_conv_params,
    const cmsis_nn_dims *input_dims,
    const cmsis_nn_dims *filter_dims
)

Get the reverse-convolution workspace size used by transpose convolution helpers.

Parameters

Parameters of arm_transpose_conv_f32_get_reverse_conv_buffer_size

Name	Type	Direction	Description
transpose_conv_params	const cmsis_nn_transpose_conv_params_f32 *	in	Transpose convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.

Returns

Returns of arm_transpose_conv_f32_get_reverse_conv_buffer_size

Description
Required buffer size in bytes, or 0 when no reverse-convolution buffer is needed.

function

arm_depthwise_nhwc_conv_f16

C

Depthwise convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:2834

arm_cmsis_nn_status arm_depthwise_nhwc_conv_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_dw_conv_params_f16 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input,
    const cmsis_nn_dims *filter_dims,
    const float16_t *kernel,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias,
    const cmsis_nn_dims *output_dims,
    float16_t *output
)

Depthwise convolution, NHWC layout.

Note

When ctx->buf is used for internal kernel repacking, it must be aligned to the element type stored in scratch: at least 4-byte aligned for float32_t and at least 2-byte aligned for float16_t.

Note

Accumulation and NaN, per leg (AmbiqAI/ns-cmsis-nn#448). Every route accumulates the bias and every tap in float32 on every leg. A NaN input tap or weight does not propagate: the ch_mult == 1 direct kernel’s MVE leg clamps it to the activation minimum (vmaxnm / vminnm); the MVE to-convolution route (input channels 1, output channels 8 or more, ctx supplied) clamps it to the activation minimum (arm_nn_clamp_mve_f32); its scalar leg and the ch_mult > 1 generic kernel clamp it to the activation maximum (ARM_NN_CLAMP). That is the pre-#448 behavior of these routes; unifying it with the float16 scalar leg under the #334 promise is a separate issue.

Note

Accumulation and NaN, per leg (AmbiqAI/ns-cmsis-nn#448, #830). Every leg accumulates every in-range tap in float32, starting from the bias, in tap order (ky, then kx), and rounds the sum to float16 once, before the clamp. A product of two halves is exact in float32, so an output differs from the exactly rounded sum only by the float32 rounding of its partial sums; where those are exact it is that sum rounded to float16. The routes are the ch_mult == 1 direct kernel, on MVE float builds (ARM_MATH_MVE_FLOAT16 without ARM_MATH_AUTOVECTORIZE) the one-input-channel kernel when ctx holds what that route requires, and the generic kernel; none reads scratch. The exact-shape kernels (1D-k3, 2x5) and the to-convolution route serve only the _acc16 entry. On MVE float builds these routes widen halves to float32 exactly whatever FPSCR.FZ16 holds, so with FZ16 set a float16 subnormal input still counts where the _acc16 entry’s float16 arithmetic flushes it; the float16 clamp still flushes a subnormal result under FZ16. No float32 partial of halves is subnormal. Under -ffast-math (the library’s -Ofast) a compiler may reorder a scalar float32 sum, which can change a result only where a partial sum is inexact. NaN: on MVE builds the direct and one-input-channel kernels clamp it to the activation minimum (vmaxnm / vminnm) and the generic kernel to the maximum (arm_nn_clamp_f16h), so a 2x5 layer with ch_mult > 1, which took the 2x5 kernel before #830, now clamps it to the maximum; on the scalar legs the direct kernel propagates it (arm_nn_clamp_scalar_f16) and the generic kernel clamps it to the maximum. Unifying these under the #334 promise is a separate issue.

Parameters

Parameters of arm_depthwise_nhwc_conv_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
dw_conv_params	const cmsis_nn_dw_conv_params_f16 *	in	Depthwise convolution parameters (stride, padding, dilation, channel multiplier and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions in NHWC format.
input	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions in NHWC-compatible depthwise format.
kernel	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions in NHWC format.
output	float16_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_depthwise_nhwc_conv_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_depthwise_nhwc_conv_f16_acc16

C

Depthwise convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:2857

arm_cmsis_nn_status arm_depthwise_nhwc_conv_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_dw_conv_params_f16 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input,
    const cmsis_nn_dims *filter_dims,
    const float16_t *kernel,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias,
    const cmsis_nn_dims *output_dims,
    float16_t *output
)

Depthwise convolution, NHWC layout.

Note

When ctx->buf is used for internal kernel repacking, it must be aligned to the element type stored in scratch: at least 4-byte aligned for float32_t and at least 2-byte aligned for float16_t.

Note

Accumulation and NaN, per leg (AmbiqAI/ns-cmsis-nn#448). Every route accumulates the bias and every tap in float32 on every leg. A NaN input tap or weight does not propagate: the ch_mult == 1 direct kernel’s MVE leg clamps it to the activation minimum (vmaxnm / vminnm); the MVE to-convolution route (input channels 1, output channels 8 or more, ctx supplied) clamps it to the activation minimum (arm_nn_clamp_mve_f32); its scalar leg and the ch_mult > 1 generic kernel clamp it to the activation maximum (ARM_NN_CLAMP). That is the pre-#448 behavior of these routes; unifying it with the float16 scalar leg under the #334 promise is a separate issue.

Note

Accumulation and NaN, per leg (AmbiqAI/ns-cmsis-nn#448, #830). Every leg accumulates every in-range tap in float32, starting from the bias, in tap order (ky, then kx), and rounds the sum to float16 once, before the clamp. A product of two halves is exact in float32, so an output differs from the exactly rounded sum only by the float32 rounding of its partial sums; where those are exact it is that sum rounded to float16. The routes are the ch_mult == 1 direct kernel, on MVE float builds (ARM_MATH_MVE_FLOAT16 without ARM_MATH_AUTOVECTORIZE) the one-input-channel kernel when ctx holds what that route requires, and the generic kernel; none reads scratch. The exact-shape kernels (1D-k3, 2x5) and the to-convolution route serve only the _acc16 entry. On MVE float builds these routes widen halves to float32 exactly whatever FPSCR.FZ16 holds, so with FZ16 set a float16 subnormal input still counts where the _acc16 entry’s float16 arithmetic flushes it; the float16 clamp still flushes a subnormal result under FZ16. No float32 partial of halves is subnormal. Under -ffast-math (the library’s -Ofast) a compiler may reorder a scalar float32 sum, which can change a result only where a partial sum is inexact. NaN: on MVE builds the direct and one-input-channel kernels clamp it to the activation minimum (vmaxnm / vminnm) and the generic kernel to the maximum (arm_nn_clamp_f16h), so a 2x5 layer with ch_mult > 1, which took the 2x5 kernel before #830, now clamps it to the maximum; on the scalar legs the direct kernel propagates it (arm_nn_clamp_scalar_f16) and the generic kernel clamps it to the maximum. Unifying these under the #334 promise is a separate issue.

Note

Float16-lane entry, the fast path (AmbiqAI/ns-cmsis-nn#586, #830): on MVE float builds every route accumulates in float16 lanes from the bias with no fold, as arm_depthwise_nhwc_conv_f16 did before #586, for callers that trade accuracy for speed. On windows of at most 32 taps that is also what the default entry gave before #830. Under -ffast-math (the library’s -Ofast) a compiler may vectorize a kernel row of the generic kernel and reorder its float16 sum at any window size (AmbiqAI/ns-cmsis-nn#693). Its scalar legs accumulate in float32 as the default entry’s do, but take the exact-shape kernels too, whose 2x5 loop orders taps column by column and clamps before rounding. Same arguments, scratch buffer (and sizer) and return codes as arm_depthwise_nhwc_conv_f16.

Parameters

Parameters of arm_depthwise_nhwc_conv_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
dw_conv_params	const cmsis_nn_dw_conv_params_f16 *	in	Depthwise convolution parameters (stride, padding, dilation, channel multiplier and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions in NHWC format.
input	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions in NHWC-compatible depthwise format.
kernel	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions in NHWC format.
output	float16_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_depthwise_nhwc_conv_f16_acc16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_depthwise_conv_generic_nhwc_f16

C

Basic float16 depthwise convolution, NHWC, on the generic route of armdepthwiseconvf16(), as a direct entry: any layer, no scratch.

Include/arm_nnfunctions_flt.h:2894

arm_cmsis_nn_status arm_depthwise_conv_generic_nhwc_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_dw_conv_params_f16 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input,
    const cmsis_nn_dims *filter_dims,
    const float16_t *kernel,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias,
    const cmsis_nn_dims *output_dims,
    float16_t *output
)

Basic float16 depthwise convolution, NHWC, on the generic route of arm_depthwise_conv_f16(), as a direct entry: any layer, no scratch.

• The output is identical to arm_depthwise_conv_f16() for a layer on this route. The _acc16 entries accumulate as arm_depthwise_conv_f16_acc16() does.
• The other direct entries take the same arguments and return ARM_CMSIS_NN_NO_IMPL_ERROR, writing nothing, for a layer outside their gate (named in each entry’s note).

Parameters

Parameters of arm_depthwise_conv_generic_nhwc_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
dw_conv_params	const cmsis_nn_dw_conv_params_f16 *	in	Depthwise parameters: stride, padding, dilation, channel multiplier and activation
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN]
input	const float16_t *	in	Input data pointer. Data type: float16
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [1, HK, WK, C_OUT]
kernel	const float16_t *	in	Filter data pointer, KC layout. Data type: float16
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float16
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output	float16_t *	out	Output data pointer. Data type: float16

Returns

Returns of arm_depthwise_conv_generic_nhwc_f16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - dw_conv_params, a dimension or a data pointer other than bias is NULL `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_depthwise_conv_generic_nhwc_f16_acc16

C

Basic float16 depthwise convolution, NHWC, on the generic route of armdepthwiseconvf16(), as a direct entry: any layer, no scratch.

Include/arm_nnfunctions_flt.h:2910

arm_cmsis_nn_status arm_depthwise_conv_generic_nhwc_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_dw_conv_params_f16 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input,
    const cmsis_nn_dims *filter_dims,
    const float16_t *kernel,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias,
    const cmsis_nn_dims *output_dims,
    float16_t *output
)

Basic float16 depthwise convolution, NHWC, on the generic route of arm_depthwise_conv_f16(), as a direct entry: any layer, no scratch.

• The output is identical to arm_depthwise_conv_f16() for a layer on this route. The _acc16 entries accumulate as arm_depthwise_conv_f16_acc16() does.
• The other direct entries take the same arguments and return ARM_CMSIS_NN_NO_IMPL_ERROR, writing nothing, for a layer outside their gate (named in each entry’s note).

Note

Accumulates as arm_depthwise_conv_f16_acc16() does.

Parameters

Parameters of arm_depthwise_conv_generic_nhwc_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
dw_conv_params	const cmsis_nn_dw_conv_params_f16 *	in	Depthwise parameters: stride, padding, dilation, channel multiplier and activation
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN]
input	const float16_t *	in	Input data pointer. Data type: float16
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [1, HK, WK, C_OUT]
kernel	const float16_t *	in	Filter data pointer, KC layout. Data type: float16
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float16
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output	float16_t *	out	Output data pointer. Data type: float16

Returns

Returns of arm_depthwise_conv_generic_nhwc_f16_acc16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - dw_conv_params, a dimension or a data pointer other than bias is NULL `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_depthwise_conv_1d_k3_nhwc_f16

C

Basic float16 depthwise convolution, NHWC, on the generic route of armdepthwiseconvf16(), as a direct entry: any layer, no scratch.

Include/arm_nnfunctions_flt.h:2927

arm_cmsis_nn_status arm_depthwise_conv_1d_k3_nhwc_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_dw_conv_params_f16 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input,
    const cmsis_nn_dims *filter_dims,
    const float16_t *kernel,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias,
    const cmsis_nn_dims *output_dims,
    float16_t *output
)

Basic float16 depthwise convolution, NHWC, on the generic route of arm_depthwise_conv_f16(), as a direct entry: any layer, no scratch.

• The output is identical to arm_depthwise_conv_f16() for a layer on this route. The _acc16 entries accumulate as arm_depthwise_conv_f16_acc16() does.
• The other direct entries take the same arguments and return ARM_CMSIS_NN_NO_IMPL_ERROR, writing nothing, for a layer outside their gate (named in each entry’s note).

Note

The conv1d k3 route. Gate: arm_nn_dw_f16_is_1d_k3. On MVE float builds this entry gives the router’s float32 result for the layer; the float16-lane k3 kernel is arm_depthwise_conv_1d_k3_nhwc_f16_acc16 (#830).

Parameters

Parameters of arm_depthwise_conv_1d_k3_nhwc_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
dw_conv_params	const cmsis_nn_dw_conv_params_f16 *	in	Depthwise parameters: stride, padding, dilation, channel multiplier and activation
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN]
input	const float16_t *	in	Input data pointer. Data type: float16
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [1, HK, WK, C_OUT]
kernel	const float16_t *	in	Filter data pointer, KC layout. Data type: float16
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float16
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output	float16_t *	out	Output data pointer. Data type: float16

Returns

Returns of arm_depthwise_conv_1d_k3_nhwc_f16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - dw_conv_params, a dimension or a data pointer other than bias is NULL `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_depthwise_conv_1d_k3_nhwc_f16_acc16

C

Basic float16 depthwise convolution, NHWC, on the generic route of armdepthwiseconvf16(), as a direct entry: any layer, no scratch.

Include/arm_nnfunctions_flt.h:2943

arm_cmsis_nn_status arm_depthwise_conv_1d_k3_nhwc_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_dw_conv_params_f16 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input,
    const cmsis_nn_dims *filter_dims,
    const float16_t *kernel,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias,
    const cmsis_nn_dims *output_dims,
    float16_t *output
)

Basic float16 depthwise convolution, NHWC, on the generic route of arm_depthwise_conv_f16(), as a direct entry: any layer, no scratch.

• The output is identical to arm_depthwise_conv_f16() for a layer on this route. The _acc16 entries accumulate as arm_depthwise_conv_f16_acc16() does.
• The other direct entries take the same arguments and return ARM_CMSIS_NN_NO_IMPL_ERROR, writing nothing, for a layer outside their gate (named in each entry’s note).

Note

The conv1d k3 route, accumulating as arm_depthwise_conv_f16_acc16() does. Gate: arm_nn_dw_f16_is_1d_k3.

Parameters

Parameters of arm_depthwise_conv_1d_k3_nhwc_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
dw_conv_params	const cmsis_nn_dw_conv_params_f16 *	in	Depthwise parameters: stride, padding, dilation, channel multiplier and activation
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN]
input	const float16_t *	in	Input data pointer. Data type: float16
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [1, HK, WK, C_OUT]
kernel	const float16_t *	in	Filter data pointer, KC layout. Data type: float16
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float16
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output	float16_t *	out	Output data pointer. Data type: float16

Returns

Returns of arm_depthwise_conv_1d_k3_nhwc_f16_acc16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - dw_conv_params, a dimension or a data pointer other than bias is NULL `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_depthwise_conv_2x5_nhwc_f16

C

Basic float16 depthwise convolution, NHWC, on the generic route of armdepthwiseconvf16(), as a direct entry: any layer, no scratch.

Include/arm_nnfunctions_flt.h:2960

arm_cmsis_nn_status arm_depthwise_conv_2x5_nhwc_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_dw_conv_params_f16 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input,
    const cmsis_nn_dims *filter_dims,
    const float16_t *kernel,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias,
    const cmsis_nn_dims *output_dims,
    float16_t *output
)

Basic float16 depthwise convolution, NHWC, on the generic route of arm_depthwise_conv_f16(), as a direct entry: any layer, no scratch.

• The output is identical to arm_depthwise_conv_f16() for a layer on this route. The _acc16 entries accumulate as arm_depthwise_conv_f16_acc16() does.
• The other direct entries take the same arguments and return ARM_CMSIS_NN_NO_IMPL_ERROR, writing nothing, for a layer outside their gate (named in each entry’s note).

Note

The 2x5 route. Gate: arm_nn_dw_f16_is_2x5. On MVE float builds this entry gives the router’s float32 result for the layer; the float16-lane 2x5 kernel is arm_depthwise_conv_2x5_nhwc_f16_acc16 (#830).

Parameters

Parameters of arm_depthwise_conv_2x5_nhwc_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
dw_conv_params	const cmsis_nn_dw_conv_params_f16 *	in	Depthwise parameters: stride, padding, dilation, channel multiplier and activation
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN]
input	const float16_t *	in	Input data pointer. Data type: float16
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [1, HK, WK, C_OUT]
kernel	const float16_t *	in	Filter data pointer, KC layout. Data type: float16
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float16
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output	float16_t *	out	Output data pointer. Data type: float16

Returns

Returns of arm_depthwise_conv_2x5_nhwc_f16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - dw_conv_params, a dimension or a data pointer other than bias is NULL `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_depthwise_conv_2x5_nhwc_f16_acc16

C

Basic float16 depthwise convolution, NHWC, on the generic route of armdepthwiseconvf16(), as a direct entry: any layer, no scratch.

Include/arm_nnfunctions_flt.h:2976

arm_cmsis_nn_status arm_depthwise_conv_2x5_nhwc_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_dw_conv_params_f16 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input,
    const cmsis_nn_dims *filter_dims,
    const float16_t *kernel,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias,
    const cmsis_nn_dims *output_dims,
    float16_t *output
)

Basic float16 depthwise convolution, NHWC, on the generic route of arm_depthwise_conv_f16(), as a direct entry: any layer, no scratch.

• The output is identical to arm_depthwise_conv_f16() for a layer on this route. The _acc16 entries accumulate as arm_depthwise_conv_f16_acc16() does.
• The other direct entries take the same arguments and return ARM_CMSIS_NN_NO_IMPL_ERROR, writing nothing, for a layer outside their gate (named in each entry’s note).

Note

The 2x5 route, accumulating as arm_depthwise_conv_f16_acc16() does. Gate: arm_nn_dw_f16_is_2x5.

Parameters

Parameters of arm_depthwise_conv_2x5_nhwc_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
dw_conv_params	const cmsis_nn_dw_conv_params_f16 *	in	Depthwise parameters: stride, padding, dilation, channel multiplier and activation
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN]
input	const float16_t *	in	Input data pointer. Data type: float16
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [1, HK, WK, C_OUT]
kernel	const float16_t *	in	Filter data pointer, KC layout. Data type: float16
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float16
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output	float16_t *	out	Output data pointer. Data type: float16

Returns

Returns of arm_depthwise_conv_2x5_nhwc_f16_acc16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - dw_conv_params, a dimension or a data pointer other than bias is NULL `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_depthwise_conv_direct_nhwc_f16

C

Basic float16 depthwise convolution, NHWC, on the generic route of armdepthwiseconvf16(), as a direct entry: any layer, no scratch.

Include/arm_nnfunctions_flt.h:2992

arm_cmsis_nn_status arm_depthwise_conv_direct_nhwc_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_dw_conv_params_f16 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input,
    const cmsis_nn_dims *filter_dims,
    const float16_t *kernel,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias,
    const cmsis_nn_dims *output_dims,
    float16_t *output
)

Basic float16 depthwise convolution, NHWC, on the generic route of arm_depthwise_conv_f16(), as a direct entry: any layer, no scratch.

• The output is identical to arm_depthwise_conv_f16() for a layer on this route. The _acc16 entries accumulate as arm_depthwise_conv_f16_acc16() does.
• The other direct entries take the same arguments and return ARM_CMSIS_NN_NO_IMPL_ERROR, writing nothing, for a layer outside their gate (named in each entry’s note).

Note

The channel-multiplier-1 route. Gate: channel multiplier 1; any stride, dilation, padding and batch.

Parameters

Parameters of arm_depthwise_conv_direct_nhwc_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
dw_conv_params	const cmsis_nn_dw_conv_params_f16 *	in	Depthwise parameters: stride, padding, dilation, channel multiplier and activation
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN]
input	const float16_t *	in	Input data pointer. Data type: float16
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [1, HK, WK, C_OUT]
kernel	const float16_t *	in	Filter data pointer, KC layout. Data type: float16
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float16
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output	float16_t *	out	Output data pointer. Data type: float16

Returns

Returns of arm_depthwise_conv_direct_nhwc_f16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - dw_conv_params, a dimension or a data pointer other than bias is NULL `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_depthwise_conv_direct_nhwc_f16_acc16

C

Basic float16 depthwise convolution, NHWC, on the generic route of armdepthwiseconvf16(), as a direct entry: any layer, no scratch.

Include/arm_nnfunctions_flt.h:3008

arm_cmsis_nn_status arm_depthwise_conv_direct_nhwc_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_dw_conv_params_f16 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input,
    const cmsis_nn_dims *filter_dims,
    const float16_t *kernel,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias,
    const cmsis_nn_dims *output_dims,
    float16_t *output
)

Basic float16 depthwise convolution, NHWC, on the generic route of arm_depthwise_conv_f16(), as a direct entry: any layer, no scratch.

• The output is identical to arm_depthwise_conv_f16() for a layer on this route. The _acc16 entries accumulate as arm_depthwise_conv_f16_acc16() does.
• The other direct entries take the same arguments and return ARM_CMSIS_NN_NO_IMPL_ERROR, writing nothing, for a layer outside their gate (named in each entry’s note).

Note

The channel-multiplier-1 route, accumulating as arm_depthwise_conv_f16_acc16() does.

Parameters

Parameters of arm_depthwise_conv_direct_nhwc_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
dw_conv_params	const cmsis_nn_dw_conv_params_f16 *	in	Depthwise parameters: stride, padding, dilation, channel multiplier and activation
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN]
input	const float16_t *	in	Input data pointer. Data type: float16
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [1, HK, WK, C_OUT]
kernel	const float16_t *	in	Filter data pointer, KC layout. Data type: float16
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float16
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output	float16_t *	out	Output data pointer. Data type: float16

Returns

Returns of arm_depthwise_conv_direct_nhwc_f16_acc16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - dw_conv_params, a dimension or a data pointer other than bias is NULL `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_depthwise_conv_cin1_nhwc_f16

C

Basic float16 depthwise convolution, NHWC, on the generic route of armdepthwiseconvf16(), as a direct entry: any layer, no scratch.

Include/arm_nnfunctions_flt.h:3028

arm_cmsis_nn_status arm_depthwise_conv_cin1_nhwc_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_dw_conv_params_f16 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input,
    const cmsis_nn_dims *filter_dims,
    const float16_t *kernel,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias,
    const cmsis_nn_dims *output_dims,
    float16_t *output
)

Basic float16 depthwise convolution, NHWC, on the generic route of arm_depthwise_conv_f16(), as a direct entry: any layer, no scratch.

• The output is identical to arm_depthwise_conv_f16() for a layer on this route. The _acc16 entries accumulate as arm_depthwise_conv_f16_acc16() does.
• The other direct entries take the same arguments and return ARM_CMSIS_NN_NO_IMPL_ERROR, writing nothing, for a layer outside their gate (named in each entry’s note).

Note

The one-input-channel route, on MVE float builds (ARM_MATH_MVE_FLOAT16 without ARM_MATH_AUTOVECTORIZE; ARM_CMSIS_NN_NO_IMPL_ERROR elsewhere). Gate: arm_nn_dw_f16_is_cin1. ctx must hold at least arm_nn_dw_f16_cin1_min_ctx_size bytes (the packed filter and one patch row), 2-byte aligned; ARM_CMSIS_NN_ARG_ERROR otherwise (the router falls back to the generic route instead). This entry’s float32 kernel reads none of that ctx; the _acc16 entry packs the filter into it (#830).

Parameters

Parameters of arm_depthwise_conv_cin1_nhwc_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
dw_conv_params	const cmsis_nn_dw_conv_params_f16 *	in	Depthwise parameters: stride, padding, dilation, channel multiplier and activation
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN]
input	const float16_t *	in	Input data pointer. Data type: float16
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [1, HK, WK, C_OUT]
kernel	const float16_t *	in	Filter data pointer, KC layout. Data type: float16
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float16
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output	float16_t *	out	Output data pointer. Data type: float16

Returns

Returns of arm_depthwise_conv_cin1_nhwc_f16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - dw_conv_params, a dimension or a data pointer other than bias is NULL `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_depthwise_conv_cin1_nhwc_f16_acc16

C

Basic float16 depthwise convolution, NHWC, on the generic route of armdepthwiseconvf16(), as a direct entry: any layer, no scratch.

Include/arm_nnfunctions_flt.h:3045

arm_cmsis_nn_status arm_depthwise_conv_cin1_nhwc_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_dw_conv_params_f16 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input,
    const cmsis_nn_dims *filter_dims,
    const float16_t *kernel,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias,
    const cmsis_nn_dims *output_dims,
    float16_t *output
)

Basic float16 depthwise convolution, NHWC, on the generic route of arm_depthwise_conv_f16(), as a direct entry: any layer, no scratch.

• The output is identical to arm_depthwise_conv_f16() for a layer on this route. The _acc16 entries accumulate as arm_depthwise_conv_f16_acc16() does.
• The other direct entries take the same arguments and return ARM_CMSIS_NN_NO_IMPL_ERROR, writing nothing, for a layer outside their gate (named in each entry’s note).

Note

The one-input-channel route, accumulating as arm_depthwise_conv_f16_acc16() does; same build, gate and ctx conditions as arm_depthwise_conv_cin1_nhwc_f16.

Parameters

Parameters of arm_depthwise_conv_cin1_nhwc_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
dw_conv_params	const cmsis_nn_dw_conv_params_f16 *	in	Depthwise parameters: stride, padding, dilation, channel multiplier and activation
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN]
input	const float16_t *	in	Input data pointer. Data type: float16
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [1, HK, WK, C_OUT]
kernel	const float16_t *	in	Filter data pointer, KC layout. Data type: float16
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float16
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output	float16_t *	out	Output data pointer. Data type: float16

Returns

Returns of arm_depthwise_conv_cin1_nhwc_f16_acc16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - dw_conv_params, a dimension or a data pointer other than bias is NULL `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_depthwise_conv_f16

C

Depthwise convolution, dispatch by layout.

Include/arm_nnfunctions_flt.h:3076

arm_cmsis_nn_status arm_depthwise_conv_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_dw_conv_params_f16 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input,
    const cmsis_nn_dims *filter_dims,
    const float16_t *kernel,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias,
    const cmsis_nn_dims *output_dims,
    float16_t *output,
    arm_nn_tensor_layout layout
)

Depthwise convolution, dispatch by layout.

Note

When ctx->buf is used for internal kernel repacking, it must be aligned to the element type stored in scratch: at least 4-byte aligned for float32_t and at least 2-byte aligned for float16_t.

Note

Accumulation and NaN, per leg (AmbiqAI/ns-cmsis-nn#448). Every route accumulates the bias and every tap in float32 on every leg. A NaN input tap or weight does not propagate: the ch_mult == 1 direct kernel’s MVE leg clamps it to the activation minimum (vmaxnm / vminnm); the MVE to-convolution route (input channels 1, output channels 8 or more, ctx supplied) clamps it to the activation minimum (arm_nn_clamp_mve_f32); its scalar leg and the ch_mult > 1 generic kernel clamp it to the activation maximum (ARM_NN_CLAMP). That is the pre-#448 behavior of these routes; unifying it with the float16 scalar leg under the #334 promise is a separate issue.

Note

Accumulation and NaN, per leg (AmbiqAI/ns-cmsis-nn#448, #830). Every leg accumulates every in-range tap in float32, starting from the bias, in tap order (ky, then kx), and rounds the sum to float16 once, before the clamp. A product of two halves is exact in float32, so an output differs from the exactly rounded sum only by the float32 rounding of its partial sums; where those are exact it is that sum rounded to float16. The routes are the ch_mult == 1 direct kernel, on MVE float builds (ARM_MATH_MVE_FLOAT16 without ARM_MATH_AUTOVECTORIZE) the one-input-channel kernel when ctx holds what that route requires, and the generic kernel; none reads scratch. The exact-shape kernels (1D-k3, 2x5) and the to-convolution route serve only the _acc16 entry. On MVE float builds these routes widen halves to float32 exactly whatever FPSCR.FZ16 holds, so with FZ16 set a float16 subnormal input still counts where the _acc16 entry’s float16 arithmetic flushes it; the float16 clamp still flushes a subnormal result under FZ16. No float32 partial of halves is subnormal. Under -ffast-math (the library’s -Ofast) a compiler may reorder a scalar float32 sum, which can change a result only where a partial sum is inexact. NaN: on MVE builds the direct and one-input-channel kernels clamp it to the activation minimum (vmaxnm / vminnm) and the generic kernel to the maximum (arm_nn_clamp_f16h), so a 2x5 layer with ch_mult > 1, which took the 2x5 kernel before #830, now clamps it to the maximum; on the scalar legs the direct kernel propagates it (arm_nn_clamp_scalar_f16) and the generic kernel clamps it to the maximum. Unifying these under the #334 promise is a separate issue.

Parameters

Parameters of arm_depthwise_conv_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
dw_conv_params	const cmsis_nn_dw_conv_params_f16 *	in	Depthwise convolution parameters (stride, padding, dilation, channel multiplier and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format depends on `layout`.
input	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format depends on `layout`.
kernel	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format depends on `layout`.
output	float16_t *	out	Pointer to the output tensor data.
layout	arm_nn_tensor_layout	in	Tensor layout selector. Current float APIs require `ARM_NN_LAYOUT_NHWC`.

Returns

Returns of arm_depthwise_conv_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_depthwise_conv_f16_acc16

C

Depthwise convolution, dispatch by layout.

Include/arm_nnfunctions_flt.h:3100

arm_cmsis_nn_status arm_depthwise_conv_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_dw_conv_params_f16 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input,
    const cmsis_nn_dims *filter_dims,
    const float16_t *kernel,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias,
    const cmsis_nn_dims *output_dims,
    float16_t *output,
    arm_nn_tensor_layout layout
)

Depthwise convolution, dispatch by layout.

Note

When ctx->buf is used for internal kernel repacking, it must be aligned to the element type stored in scratch: at least 4-byte aligned for float32_t and at least 2-byte aligned for float16_t.

Note

Accumulation and NaN, per leg (AmbiqAI/ns-cmsis-nn#448). Every route accumulates the bias and every tap in float32 on every leg. A NaN input tap or weight does not propagate: the ch_mult == 1 direct kernel’s MVE leg clamps it to the activation minimum (vmaxnm / vminnm); the MVE to-convolution route (input channels 1, output channels 8 or more, ctx supplied) clamps it to the activation minimum (arm_nn_clamp_mve_f32); its scalar leg and the ch_mult > 1 generic kernel clamp it to the activation maximum (ARM_NN_CLAMP). That is the pre-#448 behavior of these routes; unifying it with the float16 scalar leg under the #334 promise is a separate issue.

Note

Accumulation and NaN, per leg (AmbiqAI/ns-cmsis-nn#448, #830). Every leg accumulates every in-range tap in float32, starting from the bias, in tap order (ky, then kx), and rounds the sum to float16 once, before the clamp. A product of two halves is exact in float32, so an output differs from the exactly rounded sum only by the float32 rounding of its partial sums; where those are exact it is that sum rounded to float16. The routes are the ch_mult == 1 direct kernel, on MVE float builds (ARM_MATH_MVE_FLOAT16 without ARM_MATH_AUTOVECTORIZE) the one-input-channel kernel when ctx holds what that route requires, and the generic kernel; none reads scratch. The exact-shape kernels (1D-k3, 2x5) and the to-convolution route serve only the _acc16 entry. On MVE float builds these routes widen halves to float32 exactly whatever FPSCR.FZ16 holds, so with FZ16 set a float16 subnormal input still counts where the _acc16 entry’s float16 arithmetic flushes it; the float16 clamp still flushes a subnormal result under FZ16. No float32 partial of halves is subnormal. Under -ffast-math (the library’s -Ofast) a compiler may reorder a scalar float32 sum, which can change a result only where a partial sum is inexact. NaN: on MVE builds the direct and one-input-channel kernels clamp it to the activation minimum (vmaxnm / vminnm) and the generic kernel to the maximum (arm_nn_clamp_f16h), so a 2x5 layer with ch_mult > 1, which took the 2x5 kernel before #830, now clamps it to the maximum; on the scalar legs the direct kernel propagates it (arm_nn_clamp_scalar_f16) and the generic kernel clamps it to the maximum. Unifying these under the #334 promise is a separate issue.

Note

Float16-lane entry, the fast path (AmbiqAI/ns-cmsis-nn#586, #830): on MVE float builds every route accumulates in float16 lanes from the bias with no fold, as arm_depthwise_conv_f16 did before #586, for callers that trade accuracy for speed. On windows of at most 32 taps that is also what the default entry gave before #830. Under -ffast-math (the library’s -Ofast) a compiler may vectorize a kernel row of the generic kernel and reorder its float16 sum at any window size (AmbiqAI/ns-cmsis-nn#693). Its scalar legs accumulate in float32 as the default entry’s do, but take the exact-shape kernels too, whose 2x5 loop orders taps column by column and clamps before rounding. Same arguments, scratch buffer (and sizer) and return codes as arm_depthwise_conv_f16.

Parameters

Parameters of arm_depthwise_conv_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
dw_conv_params	const cmsis_nn_dw_conv_params_f16 *	in	Depthwise convolution parameters (stride, padding, dilation, channel multiplier and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format depends on `layout`.
input	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format depends on `layout`.
kernel	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format depends on `layout`.
output	float16_t *	out	Pointer to the output tensor data.
layout	arm_nn_tensor_layout	in	Tensor layout selector. Current float APIs require `ARM_NN_LAYOUT_NHWC`.

Returns

Returns of arm_depthwise_conv_f16_acc16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_depthwise_conv_wrapper_f16

C

Depthwise convolution wrapper using the CMSIS-NN baseline path.

Include/arm_nnfunctions_flt.h:3132

arm_cmsis_nn_status arm_depthwise_conv_wrapper_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_dw_conv_params_f16 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input,
    const cmsis_nn_dims *filter_dims,
    const float16_t *kernel,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias,
    const cmsis_nn_dims *output_dims,
    float16_t *output
)

Depthwise convolution wrapper using the CMSIS-NN baseline path.

Note

When ctx->buf is used for internal kernel repacking, it must be aligned to the element type stored in scratch: at least 4-byte aligned for float32_t and at least 2-byte aligned for float16_t.

Note

Accumulation and NaN, per leg (AmbiqAI/ns-cmsis-nn#448). Every route accumulates the bias and every tap in float32 on every leg. A NaN input tap or weight does not propagate: the ch_mult == 1 direct kernel’s MVE leg clamps it to the activation minimum (vmaxnm / vminnm); the MVE to-convolution route (input channels 1, output channels 8 or more, ctx supplied) clamps it to the activation minimum (arm_nn_clamp_mve_f32); its scalar leg and the ch_mult > 1 generic kernel clamp it to the activation maximum (ARM_NN_CLAMP). That is the pre-#448 behavior of these routes; unifying it with the float16 scalar leg under the #334 promise is a separate issue.

Note

Accumulation and NaN, per leg (AmbiqAI/ns-cmsis-nn#448, #830). Every leg accumulates every in-range tap in float32, starting from the bias, in tap order (ky, then kx), and rounds the sum to float16 once, before the clamp. A product of two halves is exact in float32, so an output differs from the exactly rounded sum only by the float32 rounding of its partial sums; where those are exact it is that sum rounded to float16. The routes are the ch_mult == 1 direct kernel, on MVE float builds (ARM_MATH_MVE_FLOAT16 without ARM_MATH_AUTOVECTORIZE) the one-input-channel kernel when ctx holds what that route requires, and the generic kernel; none reads scratch. The exact-shape kernels (1D-k3, 2x5) and the to-convolution route serve only the _acc16 entry. On MVE float builds these routes widen halves to float32 exactly whatever FPSCR.FZ16 holds, so with FZ16 set a float16 subnormal input still counts where the _acc16 entry’s float16 arithmetic flushes it; the float16 clamp still flushes a subnormal result under FZ16. No float32 partial of halves is subnormal. Under -ffast-math (the library’s -Ofast) a compiler may reorder a scalar float32 sum, which can change a result only where a partial sum is inexact. NaN: on MVE builds the direct and one-input-channel kernels clamp it to the activation minimum (vmaxnm / vminnm) and the generic kernel to the maximum (arm_nn_clamp_f16h), so a 2x5 layer with ch_mult > 1, which took the 2x5 kernel before #830, now clamps it to the maximum; on the scalar legs the direct kernel propagates it (arm_nn_clamp_scalar_f16) and the generic kernel clamps it to the maximum. Unifying these under the #334 promise is a separate issue.

Parameters

Parameters of arm_depthwise_conv_wrapper_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
dw_conv_params	const cmsis_nn_dw_conv_params_f16 *	in	Depthwise convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
input	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
kernel	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions.
output	float16_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_depthwise_conv_wrapper_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_depthwise_conv_wrapper_f16_acc16

C

Depthwise convolution wrapper using the CMSIS-NN baseline path.

Include/arm_nnfunctions_flt.h:3155

arm_cmsis_nn_status arm_depthwise_conv_wrapper_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_dw_conv_params_f16 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input,
    const cmsis_nn_dims *filter_dims,
    const float16_t *kernel,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias,
    const cmsis_nn_dims *output_dims,
    float16_t *output
)

Depthwise convolution wrapper using the CMSIS-NN baseline path.

Note

When ctx->buf is used for internal kernel repacking, it must be aligned to the element type stored in scratch: at least 4-byte aligned for float32_t and at least 2-byte aligned for float16_t.

Note

Accumulation and NaN, per leg (AmbiqAI/ns-cmsis-nn#448). Every route accumulates the bias and every tap in float32 on every leg. A NaN input tap or weight does not propagate: the ch_mult == 1 direct kernel’s MVE leg clamps it to the activation minimum (vmaxnm / vminnm); the MVE to-convolution route (input channels 1, output channels 8 or more, ctx supplied) clamps it to the activation minimum (arm_nn_clamp_mve_f32); its scalar leg and the ch_mult > 1 generic kernel clamp it to the activation maximum (ARM_NN_CLAMP). That is the pre-#448 behavior of these routes; unifying it with the float16 scalar leg under the #334 promise is a separate issue.

Note

Accumulation and NaN, per leg (AmbiqAI/ns-cmsis-nn#448, #830). Every leg accumulates every in-range tap in float32, starting from the bias, in tap order (ky, then kx), and rounds the sum to float16 once, before the clamp. A product of two halves is exact in float32, so an output differs from the exactly rounded sum only by the float32 rounding of its partial sums; where those are exact it is that sum rounded to float16. The routes are the ch_mult == 1 direct kernel, on MVE float builds (ARM_MATH_MVE_FLOAT16 without ARM_MATH_AUTOVECTORIZE) the one-input-channel kernel when ctx holds what that route requires, and the generic kernel; none reads scratch. The exact-shape kernels (1D-k3, 2x5) and the to-convolution route serve only the _acc16 entry. On MVE float builds these routes widen halves to float32 exactly whatever FPSCR.FZ16 holds, so with FZ16 set a float16 subnormal input still counts where the _acc16 entry’s float16 arithmetic flushes it; the float16 clamp still flushes a subnormal result under FZ16. No float32 partial of halves is subnormal. Under -ffast-math (the library’s -Ofast) a compiler may reorder a scalar float32 sum, which can change a result only where a partial sum is inexact. NaN: on MVE builds the direct and one-input-channel kernels clamp it to the activation minimum (vmaxnm / vminnm) and the generic kernel to the maximum (arm_nn_clamp_f16h), so a 2x5 layer with ch_mult > 1, which took the 2x5 kernel before #830, now clamps it to the maximum; on the scalar legs the direct kernel propagates it (arm_nn_clamp_scalar_f16) and the generic kernel clamps it to the maximum. Unifying these under the #334 promise is a separate issue.

Note

Float16-lane entry, the fast path (AmbiqAI/ns-cmsis-nn#586, #830): on MVE float builds every route accumulates in float16 lanes from the bias with no fold, as arm_depthwise_conv_wrapper_f16 did before #586, for callers that trade accuracy for speed. On windows of at most 32 taps that is also what the default entry gave before #830. Under -ffast-math (the library’s -Ofast) a compiler may vectorize a kernel row of the generic kernel and reorder its float16 sum at any window size (AmbiqAI/ns-cmsis-nn#693). Its scalar legs accumulate in float32 as the default entry’s do, but take the exact-shape kernels too, whose 2x5 loop orders taps column by column and clamps before rounding. Same arguments, scratch buffer (and sizer) and return codes as arm_depthwise_conv_wrapper_f16.

Parameters

Parameters of arm_depthwise_conv_wrapper_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
dw_conv_params	const cmsis_nn_dw_conv_params_f16 *	in	Depthwise convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
input	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
kernel	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions.
output	float16_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_depthwise_conv_wrapper_f16_acc16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_depthwise_conv_f16_get_buffer_size

C

Get the temporary buffer size required by depthwise convolution.

Include/arm_nnfunctions_flt.h:3171

int32_t arm_depthwise_conv_f16_get_buffer_size(
    const cmsis_nn_dw_conv_params_f16 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const cmsis_nn_dims *filter_dims,
    const cmsis_nn_dims *output_dims,
    arm_nn_tensor_layout layout
)

Get the temporary buffer size required by depthwise convolution.

Note

Only one route reads scratch: on MVE builds, an NHWC depthwise with ch_mult != 1, a single input channel and at least CONVERT_DW_CONV_WITH_ONE_INPUT_CH_AND_OUTPUT_CH_ABOVE_THRESHOLD output channels can run as a regular convolution, which needs the repacked filter, ROUND_UP(output_dims->c, 4) * filter_dims->h * filter_dims->w * sizeof(float32_t) bytes (ROUND_UP(output_dims->c, 8) and sizeof(float16_t) for _f16), plus arm_convolve_wrapper_f32_get_buffer_size for that convolution. For _f16, the added workspace is the larger of arm_convolve_wrapper_f16_get_buffer_size and one patch row of filter_dims->h * filter_dims->w * sizeof(float16_t) bytes. The query reserves that for every such layer; one an exact-shape specialization takes first runs without it, so the size is an upper bound there. Every other layer the ch_mult == 1 direct kernel and the generic kernel runs without scratch and the query returns 0 (AmbiqAI/ns-cmsis-nn#448, #625). For _f16 the convolution route serves the _acc16 entries; the default entries’ one-input-channel kernel reads none of this ctx but takes the route only when ctx holds it, and otherwise runs the generic kernel (#830).

Note

On MVE float16 builds, eligible one-input-channel routes include space for the packed filter and at least one patch row. Larger existing allocations are retained to allow processing multiple rows per step.

Parameters

Parameters of arm_depthwise_conv_f16_get_buffer_size

Name	Type	Direction	Description
dw_conv_params	const cmsis_nn_dw_conv_params_f16 *	in	Depthwise convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions.
layout	arm_nn_tensor_layout	in	Tensor layout selector.

Returns

Returns of arm_depthwise_conv_f16_get_buffer_size

Description
Required buffer size in bytes, or 0 when no scratch buffer is needed.

function

arm_depthwise_conv_wrapper_f16_get_buffer_size

C

Get the buffer size required by the depthwise convolution wrapper.

Include/arm_nnfunctions_flt.h:3180

int32_t arm_depthwise_conv_wrapper_f16_get_buffer_size(
    const cmsis_nn_dw_conv_params_f16 *dw_conv_params,
    const cmsis_nn_dims *input_dims,
    const cmsis_nn_dims *filter_dims,
    const cmsis_nn_dims *output_dims
)

Get the buffer size required by the depthwise convolution wrapper.

Parameters

Parameters of arm_depthwise_conv_wrapper_f16_get_buffer_size

Name	Type	Direction	Description
dw_conv_params	const cmsis_nn_dw_conv_params_f16 *	in	Depthwise convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions.

Returns

Returns of arm_depthwise_conv_wrapper_f16_get_buffer_size

Description
Required buffer size in bytes, or 0 when no scratch buffer is needed.

function

arm_convolve_nhwc_f16

C

Convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:3188

arm_cmsis_nn_status arm_convolve_nhwc_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

Convolution, NHWC layout.

Note

Dimensions must be nonnegative and batch/channel/filter metadata must agree. Stride and dilation are positive; padding is nonnegative. Nonempty work requires positive input spatial/filter/channel extents and representable accessed products and coordinates. Invalid arguments return ARG_ERROR without output writes. Valid zero batch or output spatial extent returns SUCCESS without tensor access. Generic output windows are explicit and out-of-input taps are clipped; an unsafe specialization is declined rather than imposing a derived output shape. Pointer validity, aliasing and allocation lengths remain the caller’s responsibility. Bias may be NULL.

Note

When conv_params->weight_format is set to ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, every convolution path, including the 1xN kernels and the generic fallback that runs without scratch, interprets filter_data as an already prepacked NTxN RHS buffer instead of the standard public filter layout.

Parameters

Parameters of arm_convolve_nhwc_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float16_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_nhwc_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_nhwc_f16_acc16

C

Convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:3207

arm_cmsis_nn_status arm_convolve_nhwc_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

Convolution, NHWC layout.

Note

Dimensions must be nonnegative and batch/channel/filter metadata must agree. Stride and dilation are positive; padding is nonnegative. Nonempty work requires positive input spatial/filter/channel extents and representable accessed products and coordinates. Invalid arguments return ARG_ERROR without output writes. Valid zero batch or output spatial extent returns SUCCESS without tensor access. Generic output windows are explicit and out-of-input taps are clipped; an unsafe specialization is declined rather than imposing a derived output shape. Pointer validity, aliasing and allocation lengths remain the caller’s responsibility. Bias may be NULL.

Note

When conv_params->weight_format is set to ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, every convolution path, including the 1xN kernels and the generic fallback that runs without scratch, interprets filter_data as an already prepacked NTxN RHS buffer instead of the standard public filter layout.

Note

Float16-lane entry (AmbiqAI/ns-cmsis-nn#586): the MVE legs run with no blockwise fold, exactly as arm_convolve_nhwc_f16 did before #586 (float16 accumulator lanes wherever it used them), for callers that trade accuracy on long reductions for speed. Same arguments, scratch buffer (and sizer), return codes and scalar leg as arm_convolve_nhwc_f16.

Parameters

Parameters of arm_convolve_nhwc_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float16_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_nhwc_f16_acc16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_f16

C

Convolution, dispatch by layout.

Include/arm_nnfunctions_flt.h:3245

arm_cmsis_nn_status arm_convolve_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data,
    arm_nn_tensor_layout layout
)

Convolution, dispatch by layout.

Note

When conv_params->weight_format is set to ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, every convolution path, including the 1xN kernels and the generic fallback that runs without scratch, interprets filter_data as an already prepacked NTxN RHS buffer instead of the standard public filter layout.

Note

Accumulation width per leg. Scalar leg (non-MVE builds and ARM_MATH_AUTOVECTORIZE): the direct OHWI / NT_N_PACKED fallback accumulates bias and every tap in float32 and rounds to float16 once at the store (AmbiqAI/ns-cmsis-nn#449, #457); the 1x1, 1xN and patch-GEMM paths go through arm_nn_mat_mult_nt_t_f16 / arm_nn_mat_mult_nt_n_packed_f16, whose scalar legs do the same, as do the 1xN no-padding OHWI region and the k=3 / k=5 conv1d specializations (#465). MVE leg: the direct small-C kernel accumulates in float32 (widened lanes); the direct OHWI / NT_N_PACKED fallback, every matmul-backed path (1x1, 1xN, patch-GEMM), the 1xN no-padding region and the conv1d specializations use blockwise float16 accumulation (AmbiqAI/ns-cmsis-nn#586, superseding #446’s float16-lane choice for the MVE legs): in the kernel’s own tap order an accumulator lane sums at most 32 taps in float16 (the bias, where the kernel starts from it, opens the first block), then the partial is widened exactly and added into a float32 accumulator; the float32 sum rounds to float16 once, before the clamp. An accumulator of at most 32 taps gives exactly the float16-lane result. The _acc16 entry keeps float16 lanes throughout. Where a dot product spreads its taps over the lanes of one vector (OHWI rows, the contiguous-K matmul, the conv1d k=3 / k=5 OHWI kernels), each lane’s own taps form its blocks and, once the reduction exceeds 32 taps, each block’s lanes are widened and lanes 2j and 2j+1 added in float32 into pair accumulator j (the first block sets it); the four pair accumulators are summed once as (0+1) + (2+3), the bias is added in float32 and the total rounds once. The k=3 / k=5 kernels close a block on a whole input-channel step (30 taps per lane). An output’s taps are the ones its kernel multiplies: the direct fallback skips padded taps, so an edge output counts only its in-range taps, while patch-GEMM and the 1xN padded regions multiply a zero-padded patch and count its padded taps too. Patch-GEMM runs only when ctx provides its scratch, so an edge output’s value can depend on whether ctx->buf is given. The fold’s order is fixed; the float16 reduction of a dot of at most 32 taps is left to the compiler, which may reorder it under -ffast-math, as before #586.

Parameters

Parameters of arm_convolve_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format depends on `layout`.
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format depends on `layout`.
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format depends on `layout`.
output_data	float16_t *	out	Pointer to the output tensor data.
layout	arm_nn_tensor_layout	in	Tensor layout selector. Current float APIs require `ARM_NN_LAYOUT_NHWC`.

Returns

Returns of arm_convolve_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_f16_acc16

C

Convolution, dispatch by layout.

Include/arm_nnfunctions_flt.h:3265

arm_cmsis_nn_status arm_convolve_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data,
    arm_nn_tensor_layout layout
)

Convolution, dispatch by layout.

Note

When conv_params->weight_format is set to ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, every convolution path, including the 1xN kernels and the generic fallback that runs without scratch, interprets filter_data as an already prepacked NTxN RHS buffer instead of the standard public filter layout.

Note

Accumulation width per leg. Scalar leg (non-MVE builds and ARM_MATH_AUTOVECTORIZE): the direct OHWI / NT_N_PACKED fallback accumulates bias and every tap in float32 and rounds to float16 once at the store (AmbiqAI/ns-cmsis-nn#449, #457); the 1x1, 1xN and patch-GEMM paths go through arm_nn_mat_mult_nt_t_f16 / arm_nn_mat_mult_nt_n_packed_f16, whose scalar legs do the same, as do the 1xN no-padding OHWI region and the k=3 / k=5 conv1d specializations (#465). MVE leg: the direct small-C kernel accumulates in float32 (widened lanes); the direct OHWI / NT_N_PACKED fallback, every matmul-backed path (1x1, 1xN, patch-GEMM), the 1xN no-padding region and the conv1d specializations use blockwise float16 accumulation (AmbiqAI/ns-cmsis-nn#586, superseding #446’s float16-lane choice for the MVE legs): in the kernel’s own tap order an accumulator lane sums at most 32 taps in float16 (the bias, where the kernel starts from it, opens the first block), then the partial is widened exactly and added into a float32 accumulator; the float32 sum rounds to float16 once, before the clamp. An accumulator of at most 32 taps gives exactly the float16-lane result. The _acc16 entry keeps float16 lanes throughout. Where a dot product spreads its taps over the lanes of one vector (OHWI rows, the contiguous-K matmul, the conv1d k=3 / k=5 OHWI kernels), each lane’s own taps form its blocks and, once the reduction exceeds 32 taps, each block’s lanes are widened and lanes 2j and 2j+1 added in float32 into pair accumulator j (the first block sets it); the four pair accumulators are summed once as (0+1) + (2+3), the bias is added in float32 and the total rounds once. The k=3 / k=5 kernels close a block on a whole input-channel step (30 taps per lane). An output’s taps are the ones its kernel multiplies: the direct fallback skips padded taps, so an edge output counts only its in-range taps, while patch-GEMM and the 1xN padded regions multiply a zero-padded patch and count its padded taps too. Patch-GEMM runs only when ctx provides its scratch, so an edge output’s value can depend on whether ctx->buf is given. The fold’s order is fixed; the float16 reduction of a dot of at most 32 taps is left to the compiler, which may reorder it under -ffast-math, as before #586.

Note

Float16-lane entry (AmbiqAI/ns-cmsis-nn#586): the MVE legs run with no blockwise fold, exactly as arm_convolve_f16 did before #586 (float16 accumulator lanes wherever it used them), for callers that trade accuracy on long reductions for speed. Same arguments, scratch buffer (and sizer), return codes and scalar leg as arm_convolve_f16.

Parameters

Parameters of arm_convolve_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format depends on `layout`.
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format depends on `layout`.
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format depends on `layout`.
output_data	float16_t *	out	Pointer to the output tensor data.
layout	arm_nn_tensor_layout	in	Tensor layout selector. Current float APIs require `ARM_NN_LAYOUT_NHWC`.

Returns

Returns of arm_convolve_f16_acc16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_wrapper_f16

C

Convolution wrapper using the CMSIS-NN baseline path.

Include/arm_nnfunctions_flt.h:3280

arm_cmsis_nn_status arm_convolve_wrapper_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

Convolution wrapper using the CMSIS-NN baseline path.

Parameters

Parameters of arm_convolve_wrapper_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float16_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_wrapper_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_wrapper_f16_acc16

C

Convolution wrapper using the CMSIS-NN baseline path.

Include/arm_nnfunctions_flt.h:3299

arm_cmsis_nn_status arm_convolve_wrapper_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

Convolution wrapper using the CMSIS-NN baseline path.

Note

Float16-lane entry (AmbiqAI/ns-cmsis-nn#586): the MVE legs run with no blockwise fold, exactly as arm_convolve_wrapper_f16 did before #586 (float16 accumulator lanes wherever it used them), for callers that trade accuracy on long reductions for speed. Same arguments, scratch buffer (and sizer), return codes and scalar leg as arm_convolve_wrapper_f16.

Parameters

Parameters of arm_convolve_wrapper_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float16_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_wrapper_f16_acc16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1x1_nhwc_f16

C

1x1 convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:3313

arm_cmsis_nn_status arm_convolve_1x1_nhwc_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

1x1 convolution, NHWC layout.

Parameters

Parameters of arm_convolve_1x1_nhwc_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float16_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_1x1_nhwc_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1x1_nhwc_ohwi_f16

C

1x1 convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:3332

arm_cmsis_nn_status arm_convolve_1x1_nhwc_ohwi_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

1x1 convolution, NHWC layout.

Note

For ARM_NN_WEIGHT_FORMAT_STANDARD filters only, so that an image links only that format’s kernels; returns ARM_CMSIS_NN_NO_IMPL_ERROR and writes nothing for ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters. A filter other than 1x1, or any padding, returns ARM_CMSIS_NN_ARG_ERROR, as the format-agnostic function does; the filter format is checked first.

Parameters

Parameters of arm_convolve_1x1_nhwc_ohwi_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float16_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_1x1_nhwc_ohwi_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1x1_nhwc_packed_f16

C

1x1 convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:3351

arm_cmsis_nn_status arm_convolve_1x1_nhwc_packed_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

1x1 convolution, NHWC layout.

Note

For ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters only, so that an image links only that format’s kernels; returns ARM_CMSIS_NN_NO_IMPL_ERROR and writes nothing for ARM_NN_WEIGHT_FORMAT_STANDARD filters. A filter other than 1x1, or any padding, returns ARM_CMSIS_NN_ARG_ERROR, as the format-agnostic function does; the filter format is checked first.

Parameters

Parameters of arm_convolve_1x1_nhwc_packed_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float16_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_1x1_nhwc_packed_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1x1_nhwc_f16_acc16

C

1x1 convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:3370

arm_cmsis_nn_status arm_convolve_1x1_nhwc_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

1x1 convolution, NHWC layout.

Note

Float16-lane entry (AmbiqAI/ns-cmsis-nn#586): the MVE legs run with no blockwise fold, exactly as arm_convolve_1x1_nhwc_f16 did before #586 (float16 accumulator lanes wherever it used them), for callers that trade accuracy on long reductions for speed. Same arguments, scratch buffer (and sizer), return codes and scalar leg as arm_convolve_1x1_nhwc_f16.

Parameters

Parameters of arm_convolve_1x1_nhwc_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float16_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_1x1_nhwc_f16_acc16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1x1_nhwc_ohwi_f16_acc16

C

1x1 convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:3389

arm_cmsis_nn_status arm_convolve_1x1_nhwc_ohwi_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

1x1 convolution, NHWC layout.

Note

Float16-lane entry (AmbiqAI/ns-cmsis-nn#586): the MVE legs run with no blockwise fold, exactly as arm_convolve_1x1_nhwc_f16 did before #586 (float16 accumulator lanes wherever it used them), for callers that trade accuracy on long reductions for speed. Same arguments, scratch buffer (and sizer), return codes and scalar leg as arm_convolve_1x1_nhwc_f16.

Note

For ARM_NN_WEIGHT_FORMAT_STANDARD filters only, so that an image links only that format’s kernels; returns ARM_CMSIS_NN_NO_IMPL_ERROR and writes nothing for ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters. A filter other than 1x1, or any padding, returns ARM_CMSIS_NN_ARG_ERROR, as the format-agnostic function does; the filter format is checked first.

Parameters

Parameters of arm_convolve_1x1_nhwc_ohwi_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float16_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_1x1_nhwc_ohwi_f16_acc16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1x1_nhwc_packed_f16_acc16

C

1x1 convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:3408

arm_cmsis_nn_status arm_convolve_1x1_nhwc_packed_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

1x1 convolution, NHWC layout.

Note

Float16-lane entry (AmbiqAI/ns-cmsis-nn#586): the MVE legs run with no blockwise fold, exactly as arm_convolve_1x1_nhwc_f16 did before #586 (float16 accumulator lanes wherever it used them), for callers that trade accuracy on long reductions for speed. Same arguments, scratch buffer (and sizer), return codes and scalar leg as arm_convolve_1x1_nhwc_f16.

Note

For ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters only, so that an image links only that format’s kernels; returns ARM_CMSIS_NN_NO_IMPL_ERROR and writes nothing for ARM_NN_WEIGHT_FORMAT_STANDARD filters. A filter other than 1x1, or any padding, returns ARM_CMSIS_NN_ARG_ERROR, as the format-agnostic function does; the filter format is checked first.

Parameters

Parameters of arm_convolve_1x1_nhwc_packed_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float16_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_1x1_nhwc_packed_f16_acc16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1x1_f16

C

1x1 convolution, dispatch by layout.

Include/arm_nnfunctions_flt.h:3422

arm_cmsis_nn_status arm_convolve_1x1_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data,
    arm_nn_tensor_layout layout
)

1x1 convolution, dispatch by layout.

Note

When conv_params->weight_format is set to ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, the matmul-backed 1x1 convolution paths interpret filter_data as an already prepacked NTxN RHS buffer instead of the standard public filter layout.

Parameters

Parameters of arm_convolve_1x1_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format depends on `layout`.
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format depends on `layout`.
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format depends on `layout`.
output_data	float16_t *	out	Pointer to the output tensor data.
layout	arm_nn_tensor_layout	in	Tensor layout selector. Current float APIs require `ARM_NN_LAYOUT_NHWC`.

Returns

Returns of arm_convolve_1x1_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1x1_f16_acc16

C

1x1 convolution, dispatch by layout.

Include/arm_nnfunctions_flt.h:3442

arm_cmsis_nn_status arm_convolve_1x1_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data,
    arm_nn_tensor_layout layout
)

1x1 convolution, dispatch by layout.

Note

When conv_params->weight_format is set to ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, the matmul-backed 1x1 convolution paths interpret filter_data as an already prepacked NTxN RHS buffer instead of the standard public filter layout.

Note

Float16-lane entry (AmbiqAI/ns-cmsis-nn#586): the MVE legs run with no blockwise fold, exactly as arm_convolve_1x1_f16 did before #586 (float16 accumulator lanes wherever it used them), for callers that trade accuracy on long reductions for speed. Same arguments, scratch buffer (and sizer), return codes and scalar leg as arm_convolve_1x1_f16.

Parameters

Parameters of arm_convolve_1x1_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format depends on `layout`.
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format depends on `layout`.
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format depends on `layout`.
output_data	float16_t *	out	Pointer to the output tensor data.
layout	arm_nn_tensor_layout	in	Tensor layout selector. Current float APIs require `ARM_NN_LAYOUT_NHWC`.

Returns

Returns of arm_convolve_1x1_f16_acc16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1_x_n_nhwc_f16

C

1xN convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:3457

arm_cmsis_nn_status arm_convolve_1_x_n_nhwc_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

1xN convolution, NHWC layout.

Note

When conv_params->weight_format is set to ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, filter_data is interpreted as an already prepacked NTxN RHS buffer instead of the standard public filter layout. Every output position, including the no-pad middle region that OHWI filters take straight from the input, is then packed into scratch and multiplied by the format-aware matmul, so a packed 1xN layer with little or no padding runs slower than its OHWI equivalent.

Note

On MVE builds, with OHWI filters, the no-padding positions run row by row, read in place, through the contiguous-K matmul when the layer has at least 4 output channels and 224 taps (filter width times input channels), and through a strided kernel otherwise. The float16 entries also do so from 80 taps when 4 to 7 output channels remain in the last 8-channel block.

Parameters

Parameters of arm_convolve_1_x_n_nhwc_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float16_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_1_x_n_nhwc_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1_x_n_nhwc_ohwi_f16

C

1xN convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:3477

arm_cmsis_nn_status arm_convolve_1_x_n_nhwc_ohwi_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

1xN convolution, NHWC layout.

Note

When conv_params->weight_format is set to ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, filter_data is interpreted as an already prepacked NTxN RHS buffer instead of the standard public filter layout. Every output position, including the no-pad middle region that OHWI filters take straight from the input, is then packed into scratch and multiplied by the format-aware matmul, so a packed 1xN layer with little or no padding runs slower than its OHWI equivalent.

Note

On MVE builds, with OHWI filters, the no-padding positions run row by row, read in place, through the contiguous-K matmul when the layer has at least 4 output channels and 224 taps (filter width times input channels), and through a strided kernel otherwise. The float16 entries also do so from 80 taps when 4 to 7 output channels remain in the last 8-channel block.

Note

For ARM_NN_WEIGHT_FORMAT_STANDARD filters only, so that an image links only that format’s kernels; returns ARM_CMSIS_NN_NO_IMPL_ERROR and writes nothing for ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters. A missing ctx, a layer that is not 1xN or an input depth that differs from the filter’s returns ARM_CMSIS_NN_ARG_ERROR before the filter format is checked, and a ctx smaller than the size query returns it after; as the format-agnostic function does.

Parameters

Parameters of arm_convolve_1_x_n_nhwc_ohwi_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float16_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_1_x_n_nhwc_ohwi_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1_x_n_nhwc_packed_f16

C

1xN convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:3497

arm_cmsis_nn_status arm_convolve_1_x_n_nhwc_packed_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

1xN convolution, NHWC layout.

Note

When conv_params->weight_format is set to ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, filter_data is interpreted as an already prepacked NTxN RHS buffer instead of the standard public filter layout. Every output position, including the no-pad middle region that OHWI filters take straight from the input, is then packed into scratch and multiplied by the format-aware matmul, so a packed 1xN layer with little or no padding runs slower than its OHWI equivalent.

Note

On MVE builds, with OHWI filters, the no-padding positions run row by row, read in place, through the contiguous-K matmul when the layer has at least 4 output channels and 224 taps (filter width times input channels), and through a strided kernel otherwise. The float16 entries also do so from 80 taps when 4 to 7 output channels remain in the last 8-channel block.

Note

For ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters only, so that an image links only that format’s kernels; returns ARM_CMSIS_NN_NO_IMPL_ERROR and writes nothing for ARM_NN_WEIGHT_FORMAT_STANDARD filters. A missing ctx, a layer that is not 1xN or an input depth that differs from the filter’s returns ARM_CMSIS_NN_ARG_ERROR before the filter format is checked, and a ctx smaller than the size query returns it after; as the format-agnostic function does.

Parameters

Parameters of arm_convolve_1_x_n_nhwc_packed_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float16_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_1_x_n_nhwc_packed_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1_x_n_nhwc_f16_acc16

C

1xN convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:3516

arm_cmsis_nn_status arm_convolve_1_x_n_nhwc_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

1xN convolution, NHWC layout.

Note

When conv_params->weight_format is set to ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, filter_data is interpreted as an already prepacked NTxN RHS buffer instead of the standard public filter layout. Every output position, including the no-pad middle region that OHWI filters take straight from the input, is then packed into scratch and multiplied by the format-aware matmul, so a packed 1xN layer with little or no padding runs slower than its OHWI equivalent.

Note

On MVE builds, with OHWI filters, the no-padding positions run row by row, read in place, through the contiguous-K matmul when the layer has at least 4 output channels and 224 taps (filter width times input channels), and through a strided kernel otherwise. The float16 entries also do so from 80 taps when 4 to 7 output channels remain in the last 8-channel block.

Note

Float16-lane entry (AmbiqAI/ns-cmsis-nn#586): the MVE legs run with no blockwise fold, exactly as arm_convolve_1_x_n_nhwc_f16 did before #586 (float16 accumulator lanes wherever it used them), for callers that trade accuracy on long reductions for speed. Same arguments, scratch buffer (and sizer), return codes and scalar leg as arm_convolve_1_x_n_nhwc_f16.

Parameters

Parameters of arm_convolve_1_x_n_nhwc_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float16_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_1_x_n_nhwc_f16_acc16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1_x_n_nhwc_ohwi_f16_acc16

C

1xN convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:3536

arm_cmsis_nn_status arm_convolve_1_x_n_nhwc_ohwi_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

1xN convolution, NHWC layout.

Note

When conv_params->weight_format is set to ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, filter_data is interpreted as an already prepacked NTxN RHS buffer instead of the standard public filter layout. Every output position, including the no-pad middle region that OHWI filters take straight from the input, is then packed into scratch and multiplied by the format-aware matmul, so a packed 1xN layer with little or no padding runs slower than its OHWI equivalent.

Note

On MVE builds, with OHWI filters, the no-padding positions run row by row, read in place, through the contiguous-K matmul when the layer has at least 4 output channels and 224 taps (filter width times input channels), and through a strided kernel otherwise. The float16 entries also do so from 80 taps when 4 to 7 output channels remain in the last 8-channel block.

Note

Float16-lane entry (AmbiqAI/ns-cmsis-nn#586): the MVE legs run with no blockwise fold, exactly as arm_convolve_1_x_n_nhwc_f16 did before #586 (float16 accumulator lanes wherever it used them), for callers that trade accuracy on long reductions for speed. Same arguments, scratch buffer (and sizer), return codes and scalar leg as arm_convolve_1_x_n_nhwc_f16.

Note

For ARM_NN_WEIGHT_FORMAT_STANDARD filters only, so that an image links only that format’s kernels; returns ARM_CMSIS_NN_NO_IMPL_ERROR and writes nothing for ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters. A missing ctx, a layer that is not 1xN or an input depth that differs from the filter’s returns ARM_CMSIS_NN_ARG_ERROR before the filter format is checked, and a ctx smaller than the size query returns it after; as the format-agnostic function does.

Parameters

Parameters of arm_convolve_1_x_n_nhwc_ohwi_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float16_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_1_x_n_nhwc_ohwi_f16_acc16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1_x_n_nhwc_packed_f16_acc16

C

1xN convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:3556

arm_cmsis_nn_status arm_convolve_1_x_n_nhwc_packed_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

1xN convolution, NHWC layout.

Note

When conv_params->weight_format is set to ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, filter_data is interpreted as an already prepacked NTxN RHS buffer instead of the standard public filter layout. Every output position, including the no-pad middle region that OHWI filters take straight from the input, is then packed into scratch and multiplied by the format-aware matmul, so a packed 1xN layer with little or no padding runs slower than its OHWI equivalent.

Note

On MVE builds, with OHWI filters, the no-padding positions run row by row, read in place, through the contiguous-K matmul when the layer has at least 4 output channels and 224 taps (filter width times input channels), and through a strided kernel otherwise. The float16 entries also do so from 80 taps when 4 to 7 output channels remain in the last 8-channel block.

Note

Float16-lane entry (AmbiqAI/ns-cmsis-nn#586): the MVE legs run with no blockwise fold, exactly as arm_convolve_1_x_n_nhwc_f16 did before #586 (float16 accumulator lanes wherever it used them), for callers that trade accuracy on long reductions for speed. Same arguments, scratch buffer (and sizer), return codes and scalar leg as arm_convolve_1_x_n_nhwc_f16.

Note

For ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters only, so that an image links only that format’s kernels; returns ARM_CMSIS_NN_NO_IMPL_ERROR and writes nothing for ARM_NN_WEIGHT_FORMAT_STANDARD filters. A missing ctx, a layer that is not 1xN or an input depth that differs from the filter’s returns ARM_CMSIS_NN_ARG_ERROR before the filter format is checked, and a ctx smaller than the size query returns it after; as the format-agnostic function does.

Parameters

Parameters of arm_convolve_1_x_n_nhwc_packed_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format: [N, H, W, C_IN].
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN].
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT].
output_data	float16_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_convolve_1_x_n_nhwc_packed_f16_acc16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1_x_n_f16

C

1xN convolution, dispatch by layout.

Include/arm_nnfunctions_flt.h:3581

arm_cmsis_nn_status arm_convolve_1_x_n_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data,
    arm_nn_tensor_layout layout
)

1xN convolution, dispatch by layout.

Note

When conv_params->weight_format is set to ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, filter_data is interpreted as an already prepacked NTxN RHS buffer instead of the standard public filter layout. Every output position, including the no-pad middle region that OHWI filters take straight from the input, is then packed into scratch and multiplied by the format-aware matmul, so a packed 1xN layer with little or no padding runs slower than its OHWI equivalent.

Note

On MVE builds, with OHWI filters, the no-padding positions run row by row, read in place, through the contiguous-K matmul when the layer has at least 4 output channels and 224 taps (filter width times input channels), and through a strided kernel otherwise. The float16 entries also do so from 80 taps when 4 to 7 output channels remain in the last 8-channel block.

Note

Accumulation width per leg. Scalar leg (non-MVE builds and ARM_MATH_AUTOVECTORIZE): bias and every product accumulate in float32 and round to float16 once (AmbiqAI/ns-cmsis-nn#449, #465). MVE leg: the padded regions go through the matmul helpers; the no-padding region goes through a strided kernel, or row by row, read in place, through the same matmul helpers (see the routing note above); all with blockwise float16 accumulation (AmbiqAI/ns-cmsis-nn#586, superseding #446’s float16-lane choice for the MVE legs): in the kernel’s own tap order an accumulator lane sums at most 32 taps in float16 (the bias, where the kernel starts from it, opens the first block), then the partial is widened exactly and added into a float32 accumulator; the float32 sum rounds to float16 once, before the clamp. An accumulator of at most 32 taps gives exactly the float16-lane result. The _acc16 entry keeps float16 lanes throughout. The padded regions multiply a zero-padded patch row, so their outputs count the padded taps as well.

Parameters

Parameters of arm_convolve_1_x_n_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format depends on `layout`.
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format depends on `layout`.
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format depends on `layout`.
output_data	float16_t *	out	Pointer to the output tensor data.
layout	arm_nn_tensor_layout	in	Tensor layout selector. Current float APIs require `ARM_NN_LAYOUT_NHWC`.

Returns

Returns of arm_convolve_1_x_n_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_1_x_n_f16_acc16

C

1xN convolution, dispatch by layout.

Include/arm_nnfunctions_flt.h:3601

arm_cmsis_nn_status arm_convolve_1_x_n_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data,
    arm_nn_tensor_layout layout
)

1xN convolution, dispatch by layout.

Note

When conv_params->weight_format is set to ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, filter_data is interpreted as an already prepacked NTxN RHS buffer instead of the standard public filter layout. Every output position, including the no-pad middle region that OHWI filters take straight from the input, is then packed into scratch and multiplied by the format-aware matmul, so a packed 1xN layer with little or no padding runs slower than its OHWI equivalent.

Note

On MVE builds, with OHWI filters, the no-padding positions run row by row, read in place, through the contiguous-K matmul when the layer has at least 4 output channels and 224 taps (filter width times input channels), and through a strided kernel otherwise. The float16 entries also do so from 80 taps when 4 to 7 output channels remain in the last 8-channel block.

Note

Accumulation width per leg. Scalar leg (non-MVE builds and ARM_MATH_AUTOVECTORIZE): bias and every product accumulate in float32 and round to float16 once (AmbiqAI/ns-cmsis-nn#449, #465). MVE leg: the padded regions go through the matmul helpers; the no-padding region goes through a strided kernel, or row by row, read in place, through the same matmul helpers (see the routing note above); all with blockwise float16 accumulation (AmbiqAI/ns-cmsis-nn#586, superseding #446’s float16-lane choice for the MVE legs): in the kernel’s own tap order an accumulator lane sums at most 32 taps in float16 (the bias, where the kernel starts from it, opens the first block), then the partial is widened exactly and added into a float32 accumulator; the float32 sum rounds to float16 once, before the clamp. An accumulator of at most 32 taps gives exactly the float16-lane result. The _acc16 entry keeps float16 lanes throughout. The padded regions multiply a zero-padded patch row, so their outputs count the padded taps as well.

Note

Float16-lane entry (AmbiqAI/ns-cmsis-nn#586): the MVE legs run with no blockwise fold, exactly as arm_convolve_1_x_n_f16 did before #586 (float16 accumulator lanes wherever it used them), for callers that trade accuracy on long reductions for speed. Same arguments, scratch buffer (and sizer), return codes and scalar leg as arm_convolve_1_x_n_f16.

Parameters

Parameters of arm_convolve_1_x_n_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in, out	Function context that may hold a temporary scratch buffer.
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters (stride, padding, dilation and activation clamp).
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions. Format depends on `layout`.
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format depends on `layout`.
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT].
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format depends on `layout`.
output_data	float16_t *	out	Pointer to the output tensor data.
layout	arm_nn_tensor_layout	in	Tensor layout selector. Current float APIs require `ARM_NN_LAYOUT_NHWC`.

Returns

Returns of arm_convolve_1_x_n_f16_acc16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_convolve_f16_get_buffer_size

C

Get the temporary buffer size required by convolution.

Include/arm_nnfunctions_flt.h:3616

int32_t arm_convolve_f16_get_buffer_size(
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const cmsis_nn_dims *filter_dims,
    const cmsis_nn_dims *output_dims,
    arm_nn_tensor_layout layout
)

Get the temporary buffer size required by convolution.

Note

When conv_params->weight_format is ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, this still reports only the temporary input/im2col scratch requirement. Any offline-packed filter storage is expected to be provided by the caller.

Parameters

Parameters of arm_convolve_f16_get_buffer_size

Name	Type	Direction	Description
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions.
layout	arm_nn_tensor_layout	in	Tensor layout selector.

Returns

Returns of arm_convolve_f16_get_buffer_size

Description
Required buffer size in bytes, or 0 when no scratch buffer is needed.

function

arm_convolve_wrapper_f16_get_buffer_size

C

Get the buffer size required by the convolution wrapper.

Include/arm_nnfunctions_flt.h:3625

int32_t arm_convolve_wrapper_f16_get_buffer_size(
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const cmsis_nn_dims *filter_dims,
    const cmsis_nn_dims *output_dims
)

Get the buffer size required by the convolution wrapper.

Parameters

Parameters of arm_convolve_wrapper_f16_get_buffer_size

Name	Type	Direction	Description
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions.

Returns

Returns of arm_convolve_wrapper_f16_get_buffer_size

Description
Required buffer size in bytes, or 0 when no scratch buffer is needed.

function

arm_convolve_1x1_f16_get_buffer_size

C

Get the buffer size required by 1x1 convolution.

Include/arm_nnfunctions_flt.h:3633

int32_t arm_convolve_1x1_f16_get_buffer_size(
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const cmsis_nn_dims *filter_dims,
    const cmsis_nn_dims *output_dims,
    arm_nn_tensor_layout layout
)

Get the buffer size required by 1x1 convolution.

Note

Returns 0 for the unity-stride no-pack path. For non-unity-stride NHWC 1x1 convolution, the returned scratch size enables the packed-tile + GEMM path. When conv_params->weight_format is ARM_NN_WEIGHT_FORMAT_NT_N_PACKED, this still excludes the offline-packed filter storage itself.

Parameters

Parameters of arm_convolve_1x1_f16_get_buffer_size

Name	Type	Direction	Description
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions.
layout	arm_nn_tensor_layout	in	Tensor layout selector.

Returns

Returns of arm_convolve_1x1_f16_get_buffer_size

Description
Required buffer size in bytes, or 0 when no scratch buffer is needed.

function

arm_convolve_1_x_n_f16_get_buffer_size

C

Get the buffer size required by 1xN convolution.

Include/arm_nnfunctions_flt.h:3642

int32_t arm_convolve_1_x_n_f16_get_buffer_size(
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const cmsis_nn_dims *filter_dims,
    const cmsis_nn_dims *output_dims,
    arm_nn_tensor_layout layout
)

Get the buffer size required by 1xN convolution.

Parameters

Parameters of arm_convolve_1_x_n_f16_get_buffer_size

Name	Type	Direction	Description
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions.
layout	arm_nn_tensor_layout	in	Tensor layout selector.

Returns

Returns of arm_convolve_1_x_n_f16_get_buffer_size

Description
Required buffer size in bytes, or 0 when no scratch buffer is needed.

function

arm_convolve_1d_k5_nhwc_ohwi_f16

C

Basic float32 conv1d with a 1x5 filter.

Include/arm_nnfunctions_flt.h:3651

arm_cmsis_nn_status arm_convolve_1d_k5_nhwc_ohwi_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

Basic float32 conv1d with a 1x5 filter.

The conv1d k5 route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry.

• Gate: arm_nn_conv_flt_is_1d_k with k = 5: batch 1, input and output height 1, a 1x5 filter, unit stride and dilation, no padding. No scratch.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_1d_k5_nhwc_ohwi_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float16_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float16_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float16_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_1d_k5_nhwc_ohwi_f16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL `ARM_CMSIS_NN_NO_IMPL_ERROR` - the layer is not the shape arm_nn_conv_flt_is_1d_k accepts with k = 5, or the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_1d_k5_nhwc_ohwi_f16_acc16

C

Basic float32 conv1d with a 1x5 filter.

Include/arm_nnfunctions_flt.h:3665

arm_cmsis_nn_status arm_convolve_1d_k5_nhwc_ohwi_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

Basic float32 conv1d with a 1x5 filter.

The conv1d k5 route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry.

• Gate: arm_nn_conv_flt_is_1d_k with k = 5: batch 1, input and output height 1, a 1x5 filter, unit stride and dilation, no padding. No scratch.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_1d_k5_nhwc_ohwi_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float16_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float16_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float16_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_1d_k5_nhwc_ohwi_f16_acc16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL `ARM_CMSIS_NN_NO_IMPL_ERROR` - the layer is not the shape arm_nn_conv_flt_is_1d_k accepts with k = 5, or the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_1d_k5_nhwc_packed_f16

C

Basic float32 conv1d with a 1x5 filter.

Include/arm_nnfunctions_flt.h:3679

arm_cmsis_nn_status arm_convolve_1d_k5_nhwc_packed_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

Basic float32 conv1d with a 1x5 filter.

The conv1d k5 route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry.

• Gate: arm_nn_conv_flt_is_1d_k with k = 5: batch 1, input and output height 1, a 1x5 filter, unit stride and dilation, no padding. No scratch.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_1d_k5_nhwc_packed_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float16_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float16_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float16_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_1d_k5_nhwc_packed_f16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL `ARM_CMSIS_NN_NO_IMPL_ERROR` - the layer is not the shape arm_nn_conv_flt_is_1d_k accepts with k = 5, or the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_1d_k5_nhwc_packed_f16_acc16

C

Basic float32 conv1d with a 1x5 filter.

Include/arm_nnfunctions_flt.h:3693

arm_cmsis_nn_status arm_convolve_1d_k5_nhwc_packed_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

Basic float32 conv1d with a 1x5 filter.

The conv1d k5 route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry.

• Gate: arm_nn_conv_flt_is_1d_k with k = 5: batch 1, input and output height 1, a 1x5 filter, unit stride and dilation, no padding. No scratch.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_1d_k5_nhwc_packed_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float16_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float16_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float16_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_1d_k5_nhwc_packed_f16_acc16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL `ARM_CMSIS_NN_NO_IMPL_ERROR` - the layer is not the shape arm_nn_conv_flt_is_1d_k accepts with k = 5, or the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_1d_k3_nhwc_ohwi_f16

C

Basic float32 conv1d with a 1x3 filter.

Include/arm_nnfunctions_flt.h:3707

arm_cmsis_nn_status arm_convolve_1d_k3_nhwc_ohwi_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

Basic float32 conv1d with a 1x3 filter.

The conv1d k3 route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry.

• Gate: arm_nn_conv_flt_is_1d_k with k = 3. No scratch.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_1d_k3_nhwc_ohwi_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float16_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float16_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float16_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_1d_k3_nhwc_ohwi_f16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL `ARM_CMSIS_NN_NO_IMPL_ERROR` - the layer is not the shape arm_nn_conv_flt_is_1d_k accepts with k = 3, or the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_1d_k3_nhwc_ohwi_f16_acc16

C

Basic float32 conv1d with a 1x3 filter.

Include/arm_nnfunctions_flt.h:3721

arm_cmsis_nn_status arm_convolve_1d_k3_nhwc_ohwi_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

Basic float32 conv1d with a 1x3 filter.

The conv1d k3 route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry.

• Gate: arm_nn_conv_flt_is_1d_k with k = 3. No scratch.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_1d_k3_nhwc_ohwi_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float16_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float16_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float16_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_1d_k3_nhwc_ohwi_f16_acc16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL `ARM_CMSIS_NN_NO_IMPL_ERROR` - the layer is not the shape arm_nn_conv_flt_is_1d_k accepts with k = 3, or the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_1d_k3_nhwc_packed_f16

C

Basic float32 conv1d with a 1x3 filter.

Include/arm_nnfunctions_flt.h:3735

arm_cmsis_nn_status arm_convolve_1d_k3_nhwc_packed_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

Basic float32 conv1d with a 1x3 filter.

The conv1d k3 route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry.

• Gate: arm_nn_conv_flt_is_1d_k with k = 3. No scratch.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_1d_k3_nhwc_packed_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float16_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float16_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float16_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_1d_k3_nhwc_packed_f16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL `ARM_CMSIS_NN_NO_IMPL_ERROR` - the layer is not the shape arm_nn_conv_flt_is_1d_k accepts with k = 3, or the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_1d_k3_nhwc_packed_f16_acc16

C

Basic float32 conv1d with a 1x3 filter.

Include/arm_nnfunctions_flt.h:3749

arm_cmsis_nn_status arm_convolve_1d_k3_nhwc_packed_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

Basic float32 conv1d with a 1x3 filter.

The conv1d k3 route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry.

• Gate: arm_nn_conv_flt_is_1d_k with k = 3. No scratch.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_1d_k3_nhwc_packed_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float16_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float16_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float16_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_1d_k3_nhwc_packed_f16_acc16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL `ARM_CMSIS_NN_NO_IMPL_ERROR` - the layer is not the shape arm_nn_conv_flt_is_1d_k accepts with k = 3, or the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_small_c_nhwc_f16

C

Basic float32 direct convolution for small input-channel counts.

Include/arm_nnfunctions_flt.h:3763

arm_cmsis_nn_status arm_convolve_small_c_nhwc_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

Basic float32 direct convolution for small input-channel counts.

The small-C route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry. Lanes are output x positions and weights are scalars.

• Gate: arm_nn_conv_f32_is_small_c or arm_nn_conv_f32_is_small_c_3x3 for float32, subject to arm_nn_conv_f32_small_c_coords_ok; arm_nn_conv_f16_is_small_c for float16. Either filter format; the format changes only the weight stride inside one kernel. No scratch. The additional float32 region uses 3x3 filters, four input channels, at most eight output channels and at least four output columns.
• arm_convolve_small_c_nhwc_f16() takes the same arguments and return codes. It accumulates in float32, the kernel both arm_convolve_f16() and arm_convolve_f16_acc16() run on this route. For 3x3 filters, 2..3 input channels and output height/width >= 32, it caches two channels of weights in a fixed 216-byte stack buffer. Other admitted shapes use the uncached kernel. Neither path needs caller scratch.

Parameters

Parameters of arm_convolve_small_c_nhwc_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float16_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float16_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float16_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_small_c_nhwc_f16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL `ARM_CMSIS_NN_NO_IMPL_ERROR` - the layer is outside the gate, or the build lacks MVE float (ARM_MATH_MVEF for float32, ARM_MATH_MVE_FLOAT16 for float16) or defines ARM_MATH_AUTOVECTORIZE; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_patch_gemm_nhwc_ohwi_f16

C

Basic float32 packed-patch GEMM convolution.

Include/arm_nnfunctions_flt.h:3777

arm_cmsis_nn_status arm_convolve_patch_gemm_nhwc_ohwi_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

Basic float32 packed-patch GEMM convolution.

The packed-patch GEMM route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry: up to ARM_NN_CONV_NHWC_PATCH_GEMM_F32_MAX_TILE_ROWS output positions at a time are packed into ctx as patch rows and multiplied with the filter.

• Valid for any NHWC layer. The router takes it when arm_nn_conv_flt_is_patch_gemm holds and ctx holds one patch row; unlike the router, the entry does not fall back to the direct route.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_patch_gemm_nhwc_ohwi_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Scratch buffer of at least one patch row (HK x WK x C_IN elements); `arm_convolve_patch_gemm_f32_get_buffer_size()` gives the size for full tiles
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float16_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float16_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float16_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_patch_gemm_nhwc_ohwi_f16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL, or ctx, ctx->buf is NULL or ctx->size is below one patch row `ARM_CMSIS_NN_NO_IMPL_ERROR` - the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_patch_gemm_nhwc_ohwi_f16_acc16

C

Basic float32 packed-patch GEMM convolution.

Include/arm_nnfunctions_flt.h:3791

arm_cmsis_nn_status arm_convolve_patch_gemm_nhwc_ohwi_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

Basic float32 packed-patch GEMM convolution.

The packed-patch GEMM route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry: up to ARM_NN_CONV_NHWC_PATCH_GEMM_F32_MAX_TILE_ROWS output positions at a time are packed into ctx as patch rows and multiplied with the filter.

• Valid for any NHWC layer. The router takes it when arm_nn_conv_flt_is_patch_gemm holds and ctx holds one patch row; unlike the router, the entry does not fall back to the direct route.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_patch_gemm_nhwc_ohwi_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Scratch buffer of at least one patch row (HK x WK x C_IN elements); `arm_convolve_patch_gemm_f32_get_buffer_size()` gives the size for full tiles
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float16_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float16_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float16_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_patch_gemm_nhwc_ohwi_f16_acc16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL, or ctx, ctx->buf is NULL or ctx->size is below one patch row `ARM_CMSIS_NN_NO_IMPL_ERROR` - the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_patch_gemm_nhwc_packed_f16

C

Basic float32 packed-patch GEMM convolution.

Include/arm_nnfunctions_flt.h:3805

arm_cmsis_nn_status arm_convolve_patch_gemm_nhwc_packed_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

Basic float32 packed-patch GEMM convolution.

The packed-patch GEMM route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry: up to ARM_NN_CONV_NHWC_PATCH_GEMM_F32_MAX_TILE_ROWS output positions at a time are packed into ctx as patch rows and multiplied with the filter.

• Valid for any NHWC layer. The router takes it when arm_nn_conv_flt_is_patch_gemm holds and ctx holds one patch row; unlike the router, the entry does not fall back to the direct route.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_patch_gemm_nhwc_packed_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Scratch buffer of at least one patch row (HK x WK x C_IN elements); `arm_convolve_patch_gemm_f32_get_buffer_size()` gives the size for full tiles
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float16_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float16_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float16_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_patch_gemm_nhwc_packed_f16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL, or ctx, ctx->buf is NULL or ctx->size is below one patch row `ARM_CMSIS_NN_NO_IMPL_ERROR` - the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_patch_gemm_nhwc_packed_f16_acc16

C

Basic float32 packed-patch GEMM convolution.

Include/arm_nnfunctions_flt.h:3819

arm_cmsis_nn_status arm_convolve_patch_gemm_nhwc_packed_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

Basic float32 packed-patch GEMM convolution.

The packed-patch GEMM route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry: up to ARM_NN_CONV_NHWC_PATCH_GEMM_F32_MAX_TILE_ROWS output positions at a time are packed into ctx as patch rows and multiplied with the filter.

• Valid for any NHWC layer. The router takes it when arm_nn_conv_flt_is_patch_gemm holds and ctx holds one patch row; unlike the router, the entry does not fall back to the direct route.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_patch_gemm_nhwc_packed_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Scratch buffer of at least one patch row (HK x WK x C_IN elements); `arm_convolve_patch_gemm_f32_get_buffer_size()` gives the size for full tiles
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float16_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float16_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float16_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_patch_gemm_nhwc_packed_f16_acc16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL, or ctx, ctx->buf is NULL or ctx->size is below one patch row `ARM_CMSIS_NN_NO_IMPL_ERROR` - the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_direct_nhwc_ohwi_f16

C

Basic float32 direct convolution.

Include/arm_nnfunctions_flt.h:3833

arm_cmsis_nn_status arm_convolve_direct_nhwc_ohwi_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

Basic float32 direct convolution.

The direct route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry: the route the routers take when no other route claims the layer.

• Valid for any NHWC layer. No scratch.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_direct_nhwc_ohwi_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float16_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float16_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float16_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_direct_nhwc_ohwi_f16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL `ARM_CMSIS_NN_NO_IMPL_ERROR` - the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_direct_nhwc_ohwi_f16_acc16

C

Basic float32 direct convolution.

Include/arm_nnfunctions_flt.h:3847

arm_cmsis_nn_status arm_convolve_direct_nhwc_ohwi_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

Basic float32 direct convolution.

The direct route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry: the route the routers take when no other route claims the layer.

• Valid for any NHWC layer. No scratch.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_direct_nhwc_ohwi_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float16_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float16_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float16_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_direct_nhwc_ohwi_f16_acc16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL `ARM_CMSIS_NN_NO_IMPL_ERROR` - the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_direct_nhwc_packed_f16

C

Basic float32 direct convolution.

Include/arm_nnfunctions_flt.h:3861

arm_cmsis_nn_status arm_convolve_direct_nhwc_packed_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

Basic float32 direct convolution.

The direct route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry: the route the routers take when no other route claims the layer.

• Valid for any NHWC layer. No scratch.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_direct_nhwc_packed_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float16_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float16_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float16_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_direct_nhwc_packed_f16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL `ARM_CMSIS_NN_NO_IMPL_ERROR` - the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_direct_nhwc_packed_f16_acc16

C

Basic float32 direct convolution.

Include/arm_nnfunctions_flt.h:3875

arm_cmsis_nn_status arm_convolve_direct_nhwc_packed_f16_acc16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

Basic float32 direct convolution.

The direct route of arm_convolve_f32() and arm_convolve_f16(), as a direct entry: the route the routers take when no other route claims the layer.

• Valid for any NHWC layer. No scratch.
• The ohwi entry takes ARM_NN_WEIGHT_FORMAT_STANDARD filters and the packed entry ARM_NN_WEIGHT_FORMAT_NT_N_PACKED filters; each returns ARM_CMSIS_NN_NO_IMPL_ERROR for the other format, so that an image links only the kernel for its format.
• The float16 entries of the same name take the same arguments and return codes; the _f16 entry accumulates as arm_convolve_f16() does and the _f16_acc16 entry as arm_convolve_f16_acc16() does.

Parameters

Parameters of arm_convolve_direct_nhwc_packed_f16_acc16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Unused
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters: stride, padding, dilation, activation and weight_format
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
input_data	const float16_t *	in	Input (activation) data pointer. Data type: float32
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
filter_data	const float16_t *	in	Filter data pointer, in the format the entry names. Data type: float32
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions. Format: [C_OUT]. Unused
bias_data	const float16_t *	in	Bias data pointer, or NULL for no bias. Data type: float32
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]
output_data	float16_t *	out	Output data pointer. Data type: float32

Returns

Returns of arm_convolve_direct_nhwc_packed_f16_acc16

Description
The function returns one of the following `ARM_CMSIS_NN_ARG_ERROR` - conv_params, a dimension or a data pointer other than bias_data is NULL `ARM_CMSIS_NN_NO_IMPL_ERROR` - the filter format is not the entry's; nothing is written `ARM_CMSIS_NN_SUCCESS` - Successful operation

function

arm_convolve_patch_gemm_f16_get_buffer_size

C

Scratch size in bytes for armconvolvepatchgemmnhwcohwif32() and packedf32(): ARMNNCONVNHWCPATCHGEMMF32MAXTILEROWS patch rows of HK x WK x CIN elements.

Include/arm_nnfunctions_flt.h:3891

int32_t arm_convolve_patch_gemm_f16_get_buffer_size(
    const cmsis_nn_conv_params_f16 *conv_params,
    const cmsis_nn_dims *input_dims,
    const cmsis_nn_dims *filter_dims,
    const cmsis_nn_dims *output_dims
)

Scratch size in bytes for arm_convolve_patch_gemm_nhwc_ohwi_f32() and _packed_f32(): ARM_NN_CONV_NHWC_PATCH_GEMM_F32_MAX_TILE_ROWS patch rows of HK x WK x C_IN elements.

Note

For the float16 entries; elements are 2 bytes.

Parameters

Parameters of arm_convolve_patch_gemm_f16_get_buffer_size

Name	Type	Direction	Description
conv_params	const cmsis_nn_conv_params_f16 *	in	Convolution parameters
input_dims	const cmsis_nn_dims *	in	Input (activation) tensor dimensions. Format: [N, H, W, C_IN]
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN]
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions. Format: [N, H, W, C_OUT]

Returns

Returns of arm_convolve_patch_gemm_f16_get_buffer_size

Description
The size in bytes, or 0 for a NULL argument, a non-positive C_IN, HK, WK or C_OUT, or a size above INT32_MAX

function

arm_transpose_conv_wrapper_f16

C

Transpose convolution wrapper using the CMSIS-NN baseline path.

Include/arm_nnfunctions_flt.h:4662

arm_cmsis_nn_status arm_transpose_conv_wrapper_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_context *output_ctx,
    const cmsis_nn_transpose_conv_params_f16 *transpose_conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data,
    arm_nn_tensor_layout layout
)

Transpose convolution wrapper using the CMSIS-NN baseline path.

Parameters

Parameters of arm_transpose_conv_wrapper_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Function context. Unused; may be NULL.
output_ctx	const cmsis_nn_context *	in	Output context. Unused; may be NULL.
transpose_conv_params	const cmsis_nn_transpose_conv_params_f16 *	in	Transpose convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions.
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions.
output_data	float16_t *	out	Pointer to the output tensor data.
layout	arm_nn_tensor_layout	in	Tensor layout selector. Current float APIs require `ARM_NN_LAYOUT_NHWC`.

Returns

Returns of arm_transpose_conv_wrapper_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_transpose_conv_nhwc_f16

C

Transpose convolution, NHWC layout.

Include/arm_nnfunctions_flt.h:4678

arm_cmsis_nn_status arm_transpose_conv_nhwc_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_context *output_ctx,
    const cmsis_nn_transpose_conv_params_f16 *transpose_conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data
)

Transpose convolution, NHWC layout.

Parameters

Parameters of arm_transpose_conv_nhwc_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Function context. Unused; may be NULL.
output_ctx	const cmsis_nn_context *	in	Output context. Unused; may be NULL.
transpose_conv_params	const cmsis_nn_transpose_conv_params_f16 *	in	Transpose convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions.
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions.
output_data	float16_t *	out	Pointer to the output tensor data.

Returns

Returns of arm_transpose_conv_nhwc_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_transpose_conv_f16

C

Transpose convolution, dispatch by layout.

Include/arm_nnfunctions_flt.h:4693

arm_cmsis_nn_status arm_transpose_conv_f16(
    const cmsis_nn_context *ctx,
    const cmsis_nn_context *output_ctx,
    const cmsis_nn_transpose_conv_params_f16 *transpose_conv_params,
    const cmsis_nn_dims *input_dims,
    const float16_t *input_data,
    const cmsis_nn_dims *filter_dims,
    const float16_t *filter_data,
    const cmsis_nn_dims *bias_dims,
    const float16_t *bias_data,
    const cmsis_nn_dims *output_dims,
    float16_t *output_data,
    arm_nn_tensor_layout layout
)

Transpose convolution, dispatch by layout.

Parameters

Parameters of arm_transpose_conv_f16

Name	Type	Direction	Description
ctx	const cmsis_nn_context *	in	Function context. Unused; may be NULL.
output_ctx	const cmsis_nn_context *	in	Output context. Unused; may be NULL.
transpose_conv_params	const cmsis_nn_transpose_conv_params_f16 *	in	Transpose convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
input_data	const float16_t *	in	Pointer to the input tensor data.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
filter_data	const float16_t *	in	Pointer to the filter tensor data.
bias_dims	const cmsis_nn_dims *	in	Bias tensor dimensions.
bias_data	const float16_t *	in	Optional bias tensor data.
output_dims	const cmsis_nn_dims *	in	Output tensor dimensions.
output_data	float16_t *	out	Pointer to the output tensor data.
layout	arm_nn_tensor_layout	in	Tensor layout selector. Current float APIs require `ARM_NN_LAYOUT_NHWC`.

Returns

Returns of arm_transpose_conv_f16

Description
`ARM_CMSIS_NN_SUCCESS` on success or `ARM_CMSIS_NN_ARG_ERROR` on invalid arguments.

function

arm_transpose_conv_f16_get_buffer_size

C

Get the temporary buffer size required by transpose convolution.

Include/arm_nnfunctions_flt.h:4709

int32_t arm_transpose_conv_f16_get_buffer_size(
    const cmsis_nn_transpose_conv_params_f16 *transpose_conv_params,
    const cmsis_nn_dims *input_dims,
    const cmsis_nn_dims *filter_dims,
    const cmsis_nn_dims *out_dims
)

Get the temporary buffer size required by transpose convolution.

Parameters

Parameters of arm_transpose_conv_f16_get_buffer_size

Name	Type	Direction	Description
transpose_conv_params	const cmsis_nn_transpose_conv_params_f16 *	in	Transpose convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.
out_dims	const cmsis_nn_dims *	in	Output tensor dimensions.

Returns

Returns of arm_transpose_conv_f16_get_buffer_size

Description
Required buffer size in bytes, or 0 when no scratch buffer is needed.

function

arm_transpose_conv_f16_get_reverse_conv_buffer_size

C

Get the reverse-convolution workspace size used by transpose convolution helpers.

Include/arm_nnfunctions_flt.h:4718

int32_t arm_transpose_conv_f16_get_reverse_conv_buffer_size(
    const cmsis_nn_transpose_conv_params_f16 *transpose_conv_params,
    const cmsis_nn_dims *input_dims,
    const cmsis_nn_dims *filter_dims
)

Get the reverse-convolution workspace size used by transpose convolution helpers.

Parameters

Parameters of arm_transpose_conv_f16_get_reverse_conv_buffer_size

Name	Type	Direction	Description
transpose_conv_params	const cmsis_nn_transpose_conv_params_f16 *	in	Transpose convolution parameters.
input_dims	const cmsis_nn_dims *	in	Input tensor dimensions.
filter_dims	const cmsis_nn_dims *	in	Filter tensor dimensions.

Returns

Returns of arm_transpose_conv_f16_get_reverse_conv_buffer_size

Description
Required buffer size in bytes, or 0 when no reverse-convolution buffer is needed.