ValidCVarNameType
PythonValidCVarNameType = Annotated[str, StringConstraints(pattern=C_IDENTIFIER_PATTERN)]Classes
| Name | Description |
|---|---|
ModuleType |
Enum representing the type of exported module. |
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ValidCVarNameTypeattributeValidModuleNameTypeattributeModuleTypeclassExported module type.ModelTypeclassModel file format.ScheduleModeclassOperator dispatch shape emitted into <prefix>model.c.OptimizationGoalclassWhat the static auto choices of the optimization knobs favor.AccumulationclassThe accumulation knob: how FP16 kernels that offer a choice accumulate.KernelChoiceclassThe kernel knob: which ns-cmsis-nn direct entry an int8 layer calls.ValidCVarNameType = Annotated[str, StringConstraints(pattern=C_IDENTIFIER_PATTERN)]ValidModuleNameType = Annotated[str, StringConstraints(pattern=MODULE_NAME_PATTERN)]Exported module type.
ModuleType()Exported module type.
Each member also answers to its lowercase name (ModuleType.cmake), an
alias of the same member; the value is the configuration spelling.
ZEPHYR: str = auto()Zephyr RTOS module, zephyr.
CMAKE: str = auto()CMake module, cmake.
NSX: str = auto()NSX module (neuralspotx build system), nsx.
CMSIS_PACK: str = auto()CMSIS-Pack distribution (Open-CMSIS-Pack .pdsc),
cmsis_pack. Experimental until its packs pass full packchk
validation.
zephyr = ZEPHYRcmake = CMAKEnsx = NSXcmsis_pack = CMSIS_PACKModel file format.
ModelType()Model file format.
Each member also answers to its lowercase name (ModelType.tflite), an
alias of the same member; the value is the configuration spelling.
TFLITE: str = auto()A LiteRT flatbuffer, by its TensorFlow Lite name, tflite.
LITERT: str = auto()A LiteRT flatbuffer, litert.
tflite = TFLITElitert = LITERTOperator dispatch shape emitted into <prefix>model.c.
ScheduleMode()Operator dispatch shape emitted into <prefix>_model.c.
Selects how model_init / model_run invoke each operator. Both modes
preserve the public ABI (signatures, status enum, lifecycle latch and
constant hydration); only the internal dispatch differs. Each member also
answers to its lowercase name (ScheduleMode.table), an alias of the
same member; the value is the configuration spelling.
TABLE: str = auto()table. Runtime function-pointer table iterated by a
for loop, with the per-node ctx->callback instrumentation
seam preserved. The integration shape for RTOS scheduling / PMU
sampling.
STATIC: str = auto()static. A straight-line sequence of direct calls to
each operator’s _run (and _init) symbol. No function-pointer
table, no loop, no indirect dispatch — the AOT-correct shape that is
fully optimizer-visible. The per-node callback seam is omitted.
table = TABLEstatic = STATICWhat the static auto choices of the optimization knobs favor.
OptimizationGoal()What the static auto choices of the optimization knobs favor.
LATENCY = 'latency'latency. Faster inference, allowing approximate values when
optimization.allow_approximate is true.
BALANCED = 'balanced'balanced. Today’s defaults: no approximate knob values,
and packed layouts where they are faster: FP32 weights, and FP16
convolution weights, whose packed lanes change only FP16 rounding.
SIZE = 'size'size. Smaller code and constants. No knob has a
size-specific value yet, so today it resolves like balanced.
ACCURACY = 'accuracy'accuracy. The most accurate value of every knob. FP16
convolution weights still pack, which is not a knob.
The accumulation knob: how FP16 kernels that offer a choice accumulate.
Accumulation()The accumulation knob: how FP16 kernels that offer a choice accumulate.
Eligible packed FP16 fully connected layers under precise use a
direct entry first released in CORE 7.41.0, with four-tap FP16 partial sums folded into FP32,
FP32 bias and one final FP16 narrowing. Other precise FC layers retain the
standard layout, where eight lanes split the reduction. fast retains
its existing layout rule and legacy entry; where its alternative applies,
it changes numerics relative to precise. No FP16 FC timing improvement
is assumed. FP16 1x1 convolution and conv1d pack at every setting (see
AmbiqAI/helia-aot#582); their accumulation is unchanged. FP16 depthwise
layers on MVE call arm_depthwise_conv_f16 under precise, which
accumulates every tap in FP32 from CORE 7.47.0
(AmbiqAI/ns-cmsis-nn#881), and arm_depthwise_conv_f16_acc16 under
fast, which keeps FP16 lanes. auto follows optimization.goal
and the approximation gate.
AUTO = 'auto'PRECISE = 'precise'FAST = 'fast'The kernel knob: which ns-cmsis-nn direct entry an int8 layer calls.
KernelChoice()The kernel knob: which ns-cmsis-nn direct entry an int8 layer calls.
specialized calls a shape-specialized direct entry where one applies
(for example arm_convolve_s8_small_cin or
arm_depthwise_conv_s8_opt_3x3 or arm_resize_bilinear_s8_pow2). generic keeps the general entry
(arm_convolve_1x1_s8_fast, arm_convolve_s8,
arm_depthwise_conv_s8_opt, and the unpacked fully connected entries),
so a model links fewer distinct kernels.
Both give identical output with ns-cmsis-nn’s default rounding. auto
follows optimization.goal.
AUTO = 'auto'SPECIALIZED = 'specialized'GENERIC = 'generic'