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Atomiq AT110 settings

The subsystem being modelled

Section titled “The subsystem being modelled”

This is a conceptual view of the AT110 NPU memory subsystem, not a complete SoC block diagram. The source architecture describes a shared RAXI/AXI fabric; the crossbar below represents that shared interconnect rather than an asserted RTL topology.

AT110 NPU memory subsystem Three NPU AXI masters connect to shared AXI fabric and SSRAM, HBLRAM, PSRAM and RRAM. Cortex-M55 is contextual. One port-1 memory is selected per experiment. NPU · MODEL FOCUS Ethos-U85 256 MACs 100 / 500 MHz 3 AXI master ports Cortex-M55 Host context; not timed AT110 AXI fabric Shared interconnect 250 MHz · 128-bit Other masters share the fabric; contention is not modelled. LOGICAL PORT 0 SSRAM On-chip working memory LOGICAL PORT 1 HBLRAM Stacked memory LOGICAL PORT 1 PSRAM Via XSPI LOGICAL PORT 1 RRAM Read-only weights
Physical connections shown conceptually; logical port labels describe the estimator. Select one port-1 memory per run.

The Ethos-U85 exposes three physical AXI masters. Vela and the FVP model two logical port classes, not three independent memory choices. The numbered-master-to-class mapping is derived, not confirmed by an integration table, so this diagram does not assign master numbers.

Select the platform and mode

Section titled “Select the platform and mode”
run:
  platform: at110
  platform_mode: ULP
Setting Choices Meaning
run.platform at110 Packaged AT110 platform
run.platform_mode ULP, HP NPU mode only, not the independent CPU mode
defaults.fvp.runtime_engine litert, helia_rt, helia_aot Runtime integration
models[].memory_placement One const/arena/cache mapping Select physical memory names
defaults.vela.arena_cache_size Byte limit Port-0 arena/cache budget passed to Vela
defaults.fvp.pmu_profile See runtime contract Counter selection
run.platform_overrides.memories Per-memory timing overrides Controlled what-if experiments

The packaged SoC definition specifies ULP at 100 MHz and HP at 500 MHz for the NPU, with a 250 MHz AXI interface for SSRAM/HBLRAM. These are source-defined settings, not a performance prediction. CPU clocks are independent and not modelled by platform_mode.

Choose a memory layout

Section titled “Choose a memory layout”
Mode Constants Arena Cache
Sram_Only SSRAM SSRAM Shares the arena region
Shared_Sram HBLRAM, PSRAM or RRAM SSRAM Shares the arena region
Dedicated_Sram HBLRAM or PSRAM Same port-1 memory Separate SSRAM region

Port 1 carries one memory technology per run. A placement cannot combine HBLRAM and PSRAM, for example. RRAM is read-only on the part: use it for constants, never a writable arena, even if a simulation configuration would accept it.

This fragment selects weights in HBLRAM and working data in SSRAM; incorporate it into a complete experiment:

models:
  - name: my_model
    source: model.tflite
    memory_placement:
      - const: hblram
        arena: ssram
        cache: ssram

Timing settings and provenance

Section titled “Timing settings and provenance”

The packaged model uses the following read timing. These are model parameters, not a claim that all values are measured memory specifications.

Memory Read latency Outstanding transactions Basis
SSRAM 120 ns 2 Fitted stand-in for port rate
HBLRAM 88 ns 12 Latency estimate; queue depth from platform source
PSRAM 152 ns 10 Unverified model parameters
RRAM 240 ns 2 Fitted stand-in for the read path

The source sets write latency equal to read latency; this is an assumption, and RRAM writes are not supported on the physical part. ports_used is a compiler modelling parameter, not the number of physically wired masters.

run.platform_overrides.memories accepts read_latency_cycles, write_latency_cycles, max_outstanding, burst_length, ports_used and bandwidth. These overrides describe a synthetic experiment. Validate the full config and preserve its revision and provenance with the results.

Terminal window
uv run helx platform show at110 --verbose
uv run helx validate config path/to/experiment.yaml

Source basis: packaged helia_npu/socs/atomiq110.yaml revision v9 and the repository AT110 platform/architecture guides. AT110 power specifications, energy coefficients and mode energy scaling are intentionally omitted from this public page.