Port mapping

helx uses two logical memory paths. Start with the physical memory you want to use; the other names describe that same path in the compiler, simulator and results.

Start with two ports

Logical path	AT110 memory	Vela name
Port 0	SSRAM	Sram
Port 1	HBLRAM, PSRAM or RRAM	Dram

Port 1 uses one memory per experiment, with HBLRAM as the default. Select PSRAM or RRAM through memory_placement. Vela’s Dram is a logical name: it does not mean that every memory on this path is physically DRAM.

These two paths are not the NPU’s physical AXI master numbers. See the AT110 block diagram for that distinction.

Decide what goes where

An experiment places three kinds of data: constants (weights), the arena (working tensors), and cache (fast storage used by Vela).

Memory mode	Constants	Arena	Cache
Sram_Only	Port 0	Port 0	Shares arena
Shared_Sram	Port 1	Port 0	Shares arena
Dedicated_Sram	Port 1	Port 1	Port 0

For example, Shared_Sram can keep weights in HBLRAM and working tensors in SSRAM. RRAM is read-only on the part, so use it only for constants.

A separate cache region exists only in Dedicated_Sram. vela.arena_cache_size bounds the port-0 budget passed to Vela. Custom placement names use const_X__arena_Y__cache_Z; the executable mode follows the constants and arena ports. See AT110 settings for configuration examples.

Translate names between tools

Use this lookup when inspecting a generated configuration or result file.

Layer	Port 0	Port 1
SoC YAML axi_port	0	1
Arm port class	AXI_SRAM	AXI_EXT
Vela memory	Sram	Dram
Vela AXI name	Axi0	Axi1
Result counter prefix	npu_sram_	npu_ext_
FVP timing adapter	TA0	TA1

The selected memory supplies the timing used by Vela and its FVP adapter. Its energy model supplies the corresponding memory-energy term; no AT110 energy coefficients are published here.

Vela configuration keys

Both paths have the same controls, with a different prefix. For example, Sram_read_latency sets port 0’s compiler latency; Dram_read_latency sets port 1’s.

Suffix after Sram_ or Dram_	Controls
clock_scale	Memory clock relative to NPU clock
ports_used	Compiler’s modelled port count
burst_length	Burst length
read_latency, write_latency	Access latency
max_reads, max_writes	Outstanding transactions

Vela also defines OnChipFlash and OffChipFlash; helx does not assign memories to these. Their summary columns remain zero.

Timing-adapter addresses

These are simulator register addresses, not AT110 physical-memory addresses.

FVP subsystem	TA0 · port 0	TA1 · port 1
Corstone-320	0x50006000	0x50006800
Corstone-300	0x48103000	0x48103200

PMU event names

Host result prefixes stay consistent across NPU families, even though the driver event names change.

NPU family	Port 0 driver events	Port 1 driver events
Ethos-U55 / U65	ETHOSU_PMU_AXI0_*	ETHOSU_PMU_AXI1_*
Ethos-U85	ETHOSU_PMU_SRAM_*	ETHOSU_PMU_EXT_*

U85 also exposes interface sub-counters. helx records npu_sram0_*, npu_ext0_* and npu_ext1_* when selected by the PMU program. It does not read SRAM1_*; the second SRAM interface’s traffic is derived from aggregate SRAM traffic minus SRAM0. See the runtime contract before comparing captures.

Physical masters (derived, not confirmed)

The Ethos-U85 exposes three AXI masters on AT110. Two of them form the SRAM class and stripe 128-byte interleaved traffic between them; the third carries EXT-class traffic (the driver’s EXT0/EXT1 sub-counters exist for configurations with two EXT interfaces). On AT110 the SRAM-class masters reach two of the three SSRAM ports and the EXT-class master reaches the HBLRAM controller. Which numbered master carries which class is derived from the SoC’s AXI performance study and from FPGA counters, not from an integration table; the AT110 architecture doc in helia-estimator carries that caveat on its interconnect row.

ports_used in the SoC file is what Vela is told, not what is wired. AT110 ships ports_used: 1 for SSRAM because FPGA counters show one SRAM-class interface carrying about 90% of SRAM reads. Vela has no model of a port saturating; what keeps it from caching weights through the busy port at HP is the generated ini presenting port 1 as no slower than port 0, and Vela 5.2 honours that only for a single-port declaration (with two ports declared it caches regardless of latency).

Modes are NPU clocks

ULP and HP name the NPU clock, 100 MHz and 500 MHz. The CPU has its own ULP / LP / HP clocks (100 / 250 / 500 MHz) selected independently; helx does not model the CPU, so LP never appears as a platform mode. Memory AXI clocks are fixed at 250 MHz (PSRAM’s XSPI bridge at 62.5 MHz), so at HP a port delivers half of what the NPU can consume per cycle.

Where each name shows up

Name	Appears in
axi_port: 0 / 1	SoC and platform YAML
Sram / Dram, Axi0 / Axi1	generated Vela ini; lowercase sram_* / dram_* in Vela’s summary columns
const / arena / cache by physical memory	config memory_placement (the idiom), results memory.*_placement, Vela ini sections named const_X__arena_Y__cache_Z
Sram_Only / Shared_Sram / Dedicated_Sram	config memory_modes (an alias for the placement it means on the platform), results run.memory_mode when the placement is one of the three, Vela ini alias sections, the runtime build’s HELX_MEMORY_MODE
npu_sram_* / npu_ext_*	result bundles (run_summary.*), energy terms sram_uj / ext_uj
AXI0 / AXI1, SRAM / EXT	PMU driver symbols in the FVP runner and captures
TA0 / TA1	FVP timing-adapter registers, ETHOSU_TA_*_0 / _1 build defines
SSRAM / HBLRAM / PSRAM / RRAM	physical memories, platform names, energy YAML